Non-Volatile Memory Device Segmentation for Voltage Drop Reduction
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Solution Overview
Problem
In non-volatile ReRAM memory devices, large memory cell arrays lead to increased wiring length, causing voltage drops that can result in malfunctions between connected memory cells, while reducing the memory cell array size decreases integration density.
Innovation Solution
The implementation of a non-volatile memory device with first and second memory cell regions arranged in a matrix configuration, where the second memory cell regions have a smaller area than the first, reducing voltage drops and maintaining integration density by using shorter bit and word lines, and incorporating a dual control circuit system to manage data operations efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a large memory cell array is arranged in the chip, then the memory capacity is increased, but the wiring length is made longer which increases voltage drop and causes malfunctions
Solution Approach 1:
The memory cell array is divided into multiple blocks (first memory cell block, second memory cell block, third memory cell block, fourth memory cell block), each with its own control circuit. This segmentation reduces wiring length within each block while maintaining large total memory capacity, thereby preventing voltage drop-induced malfunctions.
Solution Approach 2:
The patent introduces a block dimension organization where memory cells are arranged in multiple blocks along one direction and multiple strings within each block along another direction. This multi-dimensional arrangement optimizes wiring length and voltage distribution while achieving large memory capacity.
2Reliability
If the memory cell array is made smaller, then the voltage drop is reduced, but the extraction wiring and control circuit region per memory cell array are made larger which decreases the degree of integration
Solution Approach 1:
By segmenting the memory into multiple blocks with shared control circuits, the patent reduces the control circuit region per memory cell array while maintaining small block sizes that minimize voltage drop. This segmentation improves integration density compared to having separate control circuits for each small array.
Solution Approach 2:
The control circuits are designed to universally control multiple memory cell blocks. Each control circuit can manage multiple blocks, reducing the total number of control circuits needed and improving integration density while maintaining reliable voltage levels in each block.
3Quantity of substance
If a large memory cell array is arranged in the chip, then the memory capacity is increased, but the wiring length is made longer which increases power consumption
Solution Approach 1:
The memory cell array is divided into multiple blocks, each with shorter internal wiring. This segmentation reduces the total wiring length required for a given memory capacity, thereby reducing power consumption while maintaining large memory capacity through the combined blocks.
Data Source
AI summary
According to one embodiment, a non-volatile memory device includes: first memory cell regions including first wirings extending in a first direction, second wirings extending in a second direction crossing the first direction, and first memory cells provided between the first wirings and the second wirings and being capable of changing resistance state; and second memory cell regions including third wirings extending in the first direction, fourth wirings extending in the second direction crossing the first direction, and second memory cells provided between the third wirings and the fourth wirings and being capable of changing resistance state, the second memory cell region having a smaller area than the first memory cell region in top view.