Nonvolatile Memory Device Segmented Floating Gates
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Solution Overview
Problem
In multilevel NAND flash memories, the increasing proximity of memory cell transistors leads to fluctuations in threshold voltage, degrading data reliability due to floating gate capacitance effects, and existing techniques do not adequately address the need for narrow threshold voltage distribution and efficient data update speed.
Innovation Solution
A nonvolatile semiconductor memory device is designed with separate areas for n-bit and 1-bit data storage, using a controller to set 2n threshold voltages for n-bit data in one area and executing n-bit data write operations similarly for 1-bit data in another area, allowing for precise threshold voltage management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the distance between memory cell transistors is reduced to increase storage capacity, then the storage capacity is improved, but the threshold voltage fluctuates due to floating gate capacitance between adjacent transistors
Solution Approach 1:
The patent divides the memory cell transistor into multiple independent floating gates (first floating gate and second floating gate) instead of using a single shared floating gate. This segmentation isolates the capacitance effects between adjacent transistors, preventing threshold voltage fluctuation while maintaining high storage capacity through multilevel data storage
2Device complexity
If a single threshold voltage is used for each memory cell, then the device complexity is reduced, but the data reliability degrades due to threshold voltage fluctuation from adjacent cells
Solution Approach 1:
The patent assigns different functional roles to different floating gates within the same memory cell transistor. The first floating gate stores lower-bit data while the second floating gate stores upper-bit data, creating localized functional differentiation that prevents mutual interference and maintains data reliability
3Quantity of substance
If multilevel data is stored in each memory cell to increase storage capacity, then the storage capacity is improved, but the threshold voltage distribution must be greatly narrowed which degrades data reliability
Solution Approach 1:
The patent segments the threshold voltage control into multiple independent floating gates, each contributing to different bits of stored data. This allows the formation of multiple distinct threshold voltage distributions (one for each bit combination) rather than requiring a single narrow distribution, thereby maintaining data reliability while enabling multilevel storage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances data reliability and storage capacity by maintaining a narrow threshold voltage distribution and efficient data update operations, preventing read errors even as threshold voltages fluctuate over time.
Implementation Method 1
the increasing proximity of memory cell transistors leads to fluctuations in threshold voltage, degrading data reliability due to floating gate capacitance effects
Data Source
AI summary
A nonvolatile semiconductor memory device includes a nonvolatile memory including a first area which stores data for every n bits (n is a natural number of not less than 2), and a second area which stores data for every 1 bit, each of the first area and the second area including a plurality of memory cells each configured to store n-bit data on the basis of a threshold voltage, and a controller which sets 2n threshold voltages corresponding to n bits when writing n-bit data to a first memory cell included in the first area, and executes the n-bit data write operation when writing 1-bit data to a second memory cell included in the second area.