Nonvolatile Memory Erase Loop Optimization via Segmented Sensing
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Solution Overview
Problem
Current nonvolatile memory devices face inefficiencies in the erase operation process, particularly in determining whether a memory block is a fail block, which prolongs the erase loop time.
Innovation Solution
The method involves performing a sensing operation on string selection and ground selection transistors of memory blocks using selected sensing schemes, allowing for simultaneous or sequential determination of fail blocks after an erase verification operation, thereby reducing the time required for the erase loop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional erase operation is performed without sensing transistors, then the erase loop time is prolonged due to continuous verification, but performing sensing operations on all transistors increases device complexity and operation time
Solution Approach 1:
The patent divides the sensing operation into two distinct phases: a first sensing operation on string selection transistors and a second sensing operation on ground selection transistors. This segmentation allows the system to identify fail blocks more efficiently by not requiring simultaneous sensing of all transistors, thereby reducing erase loop time while managing complexity through structured verification.
Solution Approach 2:
The patent performs the first sensing operation on string selection transistors before the second sensing operation on ground selection transistors. This preliminary action allows the system to identify potential fail blocks early in the verification process, enabling optimized erase loop termination and reducing overall verification time compared to traditional simultaneous sensing approaches.
2Reliability
If sensing operations are performed on all transistors simultaneously, then fail block identification is comprehensive, but the erase operation time increases significantly
Solution Approach 1:
The patent segments the transistor sensing into two sequential operations: first on string selection transistors, then on ground selection transistors. This segmentation maintains comprehensive fail block identification capability while reducing the time required compared to simultaneous sensing of all transistors, as each sensing phase can be optimized independently.
Solution Approach 2:
By performing the first sensing operation on string selection transistors before the second sensing operation on ground selection transistors, the patent enables early identification of fail blocks. This preliminary sensing action allows the system to terminate the erase loop sooner if failures are detected, reducing overall erase operation time while maintaining reliable fail block identification.
3Adaptability or versatility
If multiple sensing schemes are implemented, then the adaptability for different memory blocks is improved, but the device complexity increases
Solution Approach 1:
The patent implements a dynamic sensing operation sequence where the control circuit selectively performs the first sensing operation on string selection transistors and the second sensing operation on ground selection transistors based on detected conditions. This dynamic approach provides adaptability for different memory block states while managing control circuit complexity through condition-based decision making rather than requiring all sensing schemes to be active simultaneously.
Data Source
AI summary
A nonvolatile memory device includes memory blocks that each include cell strings formed vertically on a substrate. The cell strings are coupled to a plurality of bit-lines. The cell strings each include memory cells connected to a string selection transistor. A method of operating the nonvolatile memory device includes performing an erase operation on a first memory block of the memory blocks in response to an erase command, performing an erase verification operation on the memory cells of the first memory block, performing a first sensing operation on the string selection transistors of each of the cell strings coupled to at least some bit-lines of the first memory block, and determining whether the first memory block is a fail block at least based on a result of the first sensing operation. The first sensing operation is based on a first sensing scheme selected among a plurality of sensing schemes.