Nonvolatile Memory Circuit with Segmented Source Regions
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Nonvolatile memory cells face performance issues during read operations due to higher capacitance between the graded source region and the substrate, and the halo region can cause read disturb problems, affecting programming and erasing efficiency.
Innovation Solution
A circuit design for nonvolatile memory cells that uses different active regions for programming/erasing and reading, with a floating gate electrode and specific transistor configurations to manage charge transfer, allowing for improved reading performance without compromising programming and erasing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a graded source region is used to reduce junction breakdown, then reliability is improved, but capacitance increases and reading speed decreases
Solution Approach 1:
The source region is segmented into a lightly-doped source (LDS) region and a heavily-doped source (HDS) region. The LDS region provides low capacitance for fast reading operations, while the HDS region provides high breakdown voltage for reliable programming operations. This segmentation allows each region to be optimized for its specific function, resolving the contradiction between reliability and speed.
2Productivity
If a halo region is used to increase electrical field near drain, then programming efficiency is improved, but read disturb problems increase
Solution Approach 1:
Instead of using a uniform halo region, the invention uses locally-doped regions with different doping concentrations at specific locations. The heavily-doped source region is placed only where needed for high breakdown voltage during programming, while the lightly-doped source region is placed where low capacitance is needed during reading. This local quality approach eliminates read disturb while maintaining programming efficiency.
3Speed
If transistor structures are designed for high frequency logic, then speed is improved, but programming and erasing efficiency decreases
Solution Approach 1:
The invention changes the doping parameters and structural parameters of the transistor to optimize for non-volatile memory operations. By adjusting the doping concentration profiles (lightly-doped vs. heavily-doped regions) and other parameters, the transistor achieves both fast reading operations and efficient programming/erasing operations, resolving the contradiction between speed and productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances reading performance while maintaining programming and erasing efficiency, reduces read disturb issues, and simplifies the manufacturing process by using a single gate electrode layer, resulting in faster and more reliable memory cells.
Implementation Method 1
a floating gate electrode and specific transistor configurations to manage charge transfer
Implementation Method 2
when changing the state of the memory cell, the second transistor would be active and no significant amount of charge carriers would be transferred
Data Source
AI summary
A circuit for a nonvolatile memory cell can include a charge-altering terminal and an output terminal. The circuit can also include a first transistor having a gate electrode that electrically floats and an active region including a current-carrying electrode, wherein the current-carrying electrode is coupled to the output terminal. The circuit can further include a second transistor having a first electrode and a second electrode, wherein the first electrode is coupled to the gate electrode of the first transistor, and the second electrode is coupled to the charge-altering terminal. When changing the state of the memory cell, the second transistor can be active and no significant amount of charge carriers are transferred between the gate electrode of the first transistor and the active region of the first transistor. Other embodiments can include the electronic device itself and a process of forming the electronic device.