Nonvolatile Memory Device With Selection Gate Overlap
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Solution Overview
Problem
Conventional semiconductor memory devices face limitations in integration degree and operational characteristics, particularly in single gate EEPROMs, due to structural limitations and increased procedural steps in stack, dual, and split gate EEPROMs, which also deteriorate integration when selection gates are added to prevent over-erase.
Innovation Solution
A nonvolatile memory device with a floating gate and a selection gate that functions as a control gate, where the selection gate overlaps with the tunneling and erase regions and is coupled by a charge blocking layer, enhancing integration and preventing over-erase without the need for additional procedural steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a selection gate is added to prevent over-erase in conventional EEPROMs, then over-erase protection is improved, but device complexity increases and integration degree deteriorates
Solution Approach 1:
The patent merges the selection gate and control gate into a single integrated structure. The selection gate is formed to overlap with both the tunneling region and erase region, allowing it to simultaneously function as a selection gate (for preventing over-erase) and as a control gate (for charge injection/extraction), thereby eliminating the need for separate gates and improving integration degree
Solution Approach 2:
The selection gate is designed to perform multiple functions: it acts as a selection gate to prevent over-erase by controlling access to the tunneling region, and simultaneously serves as a control gate for the floating gate operation during programming and erasing cycles. This multi-functionality reduces device complexity while maintaining reliability
2Device complexity
If stack, dual, or split gate EEPROM structures are used to improve integration, then integration degree is improved, but procedural steps increase and manufacturing complexity worsens
Solution Approach 1:
The patent segments the substrate into distinct functional regions: a tunneling region for charge injection during programming and an erase region for charge removal during erasing. This segmentation allows the single selection gate to effectively control different operations by overlapping with different regions, achieving high integration without complex procedural steps
Solution Approach 2:
The selection gate is positioned in a dimensional arrangement that overlaps with both the tunneling region and erase region in the vertical cross-section. This spatial arrangement in another dimension (overlap configuration) enables the gate to control multiple regions simultaneously without requiring additional procedural steps or complex stacking
3Ease of manufacture
If conventional single gate EEPROM structure is used, then manufacturing is simpler, but integration degree and operational characteristics are limited
Solution Approach 1:
The patent applies local quality by creating distinct regions with different functionalities within the same device structure. The tunneling region is optimized for charge injection during programming, while the erase region is optimized for charge removal. The selection gate is locally positioned to overlap with these regions, providing enhanced control and operational characteristics while maintaining manufacturing simplicity through the basic single-gate architecture
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly improves the integration degree and operational characteristics of the nonvolatile memory device, surpassing conventional single gate EEPROMs by allowing the selection gate to function as both a control gate and a preventer of over-erase, thereby increasing the device's performance and productivity.
Implementation Method 1
a charge blocking layer filling the gap
Data Source
AI summary
A nonvolatile memory device includes a tunneling region and an erase region formed over a substrate, a selection gate formed over the substrate to overlap with the tunneling region, a floating gate formed over the substrate to be disposed adjacent to the selection gate with a gap therebetween and to overlap with the tunneling region and the erase region, and a charge blocking layer filling the gap.