Non-Volatile Memory Selective Read Modes

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Solution Overview

Problem

Non-volatile memory technologies face a trade-off between performance and persistence, with faster volatile memories being more costly and data-integrity issues due to power loss, while larger capacity non-volatile memories have slower input/output speeds and lower performance.

Innovation Solution

Implementing selective performance level modes in non-volatile memory operation, allowing dynamic adjustment of read pulse width and refresh rates based on selected modes to optimize performance and persistence, with programmable parameters for customizable operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If non-volatile memory is used to provide large storage capacity and data persistence, then data integrity is improved, but input/output speed and performance deteriorate

Engineering Contradiction:
Improvedata integrityVSAvoidinput/output speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent implements multiple operational modes (first mode with longer read pulse width for default performance, second mode with shorter read pulse width for enhanced performance) that can be dynamically selected based on system needs. This dynamic switching allows the memory system to adapt between reliability-optimized and speed-optimized operation, resolving the contradiction between data integrity and input/output speed.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the read pulse width parameter to achieve different performance characteristics. By adjusting this physical parameter (longer pulse for reliability, shorter pulse for speed), the system can operate in different modes to balance data integrity requirements against performance requirements, directly addressing the technical contradiction.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If read pulse width is reduced to improve read latency, then performance is improved, but data persistence and reliability deteriorate

Engineering Contradiction:
Improveread latencyVSAvoiddata persistence
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system dynamically adjusts read pulse width based on the selected operational mode. In the second mode, a shorter read pulse width is used to reduce read latency and improve productivity, while in the first mode, a longer read pulse width maintains data persistence and reliability. This dynamic adjustment resolves the contradiction between read latency and data persistence.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent explicitly changes the read pulse width parameter to control read latency. By reducing this parameter in the second mode, read latency is improved, while the system accepts reduced data persistence as a trade-off that can be managed through mode selection and refresh operations.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If refresh rate is increased to maintain data integrity, then reliability is improved, but energy consumption increases

Engineering Contradiction:
Improvedata integrityVSAvoidenergy consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic refresh rate adjustment based on operational mode. In the second mode with shorter read pulse width, the system increases refresh rate to compensate for reduced data persistence, ensuring reliability is maintained despite the more aggressive performance-oriented settings. This dynamic adaptation resolves the contradiction between reliability and energy consumption by optimizing refresh operations to the actual needs of each mode.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system uses feedback from the selected operational mode to determine appropriate refresh rates. When operating in performance mode with shorter pulses, the system detects the need for more frequent refreshes and adjusts accordingly, ensuring data integrity is maintained while minimizing unnecessary refresh operations in other modes, thus balancing reliability and energy consumption.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS10163502B2Selective performance level modes of operation in a non-volatile memory
Publication Date: 2018.12.25 SK HYNIX NAND PRODUCT SOLUTIONS CORP
  • US10163502B2 patent drawing
  • US10163502B2 patent drawing
  • US10163502B2 patent drawing

AI summary

In one embodiment, a non-volatile memory is controlled in a selectable read mode in response to commands from a processor. Selectable read modes may include a default read memory mode, for example, and a performance read memory mode having a shorter read pulse and a reduced read latency than the default read memory mode, for example. In one embodiment, the performance read memory mode may also have refresh operations at an increased frequency compared to that of the default read mode. Other aspects and advantages are described.