Non-Volatile Memory Floating Gate Self-Alignment
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Solution Overview
Problem
The existing methods for manufacturing non-volatile memory face challenges such as high costs and misalignment issues in the photolithography process, leading to decreased process windows and increased operating voltages, particularly as device line widths shrink below 90 nm, affecting yield and power consumption in portable electronics.
Innovation Solution
A method involving the formation of a mask layer and isolation structure with a recession, followed by the creation of a spacer and insulating layer, which allows for self-alignment of the floating gate, reducing the need for additional photolithography steps and enhancing the process window, while increasing gate electrode coupling by controlling the thickness and width of the floating gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If photolithography process is used to pattern the doped polysilicon layer, then the non-volatile memory can be manufactured, but the cost is high and misalignment issues occur easily
Solution Approach 1:
The patent applies preliminary action by forming the floating gate conductive layer before the photolithography patterning step. The floating gate is created as a conformal layer covering the entire substrate area, eliminating the need for subsequent photolithography alignment to define its position. This preliminary formation of the floating gate structure avoids the misalignment issues that would occur if photolithography were used to pattern it later in the process.
2Productivity
If device line width is decreased below 90 nm, then the memory capacity increases, but the process window of photolithography decreases and tolerance range for misalignment decreases
Solution Approach 1:
The floating gate conductive layer is formed preliminarily as a conformal layer before photolithography, establishing the floating gate structure at a larger dimensional scale that is not constrained by the reduced process window. This allows the subsequent photolithography step to focus solely on defining the control gate and isolation structures, which can be done with tighter tolerances since the floating gate position is already predetermined by the conformal deposition process.
3Productivity
If device line width is decreased, then the gate electrode coupling between floating gate and control gate decreases, but operating voltage increases
Solution Approach 1:
The patent applies local quality by making the floating gate conductive layer thickness variable in different regions. The thickness is increased in areas where stronger coupling is needed (such as beneath the control gate) and reduced in other areas. This localized thickness variation optimizes the gate electrode coupling strength in critical regions, maintaining low operating voltage where needed while still achieving high memory capacity through the overall reduced line width design.
Data Source
AI summary
The invention is directed to a method for manufacturing a non-volatile memory. The method comprises steps of forming a mask layer on a substrate. An isolation structure is formed in the mask layer and the substrate, wherein the top surface of the isolation structure is lower than that of the mask layer and the isolation structure and the mask layer together form a recession. A spacer is formed at the sidewall of the recession and the recession is filled with an insulating layer. The mask layer and the spacer are removed and a tunneling dielectric layer is formed over the substrate. A first conductive layer is formed to fill the first opening and the isolating layer is removed to form a second opening. A gate dielectric layer and a second conductive layer are formed over the substrate sequentially. The second conductive layer and the first conductive layer are patterned.