Nonvolatile Memory Cell With Series Transistors
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Solution Overview
Problem
Current non-volatile semiconductor memory devices face limitations in achieving higher integration and operational reliability due to the constraints of storing multiple values in a single memory transistor, which leads to narrowed threshold value ranges and increased reading times.
Innovation Solution
The implementation of a non-volatile semiconductor memory device design where two control gate electrodes oppose a silicon pillar, allowing for the formation of two memory transistors in series within each memory cell, enabling the storage of multiple values without increasing manufacturing processes or device dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple values are stored in a single memory transistor, then storage capacity is improved, but threshold value range narrows and reading time increases
Solution Approach 1:
The patent divides a single memory transistor into multiple memory transistors (first and second memory transistors) within each memory cell. Each memory transistor stores a portion of the data, allowing 18 values to be stored collectively in one memory cell. This segmentation prevents the threshold value range of individual transistors from narrowing while maintaining high storage capacity.
2Quantity of substance
If multiple values are stored in a single memory transistor, then storage capacity is improved, but reading time increases
Solution Approach 1:
By segmenting the storage function across multiple memory transistors that can be read in parallel, the patent reduces the reading time compared to reading from a single transistor storing all values. The segmented structure allows for more efficient read operations while maintaining the ability to store 18 values per memory cell.
3Quantity of substance
If two memory transistors are formed in series within each memory cell, then integration capacity is improved, but device complexity increases
Solution Approach 1:
The patent merges the first and second memory transistors into a single memory cell structure, allowing two memory transistors to share common elements such as the charge storage layer and control gate electrode. This merging approach increases integration capacity while minimizing the increase in device complexity by reusing structural components.
Solution Approach 2:
The control gate electrode and charge storage layer serve multiple functions by being shared between the first and second memory transistors. This multi-functionality allows the memory cell to store more values without proportionally increasing the number of discrete components, thereby improving integration capacity while controlling complexity.
Data Source
AI summary
According to one embodiment, a nonvolatile semiconductor memory device includes a stacked body, a semiconductor pillar and a charge storage layer. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. The semiconductor pillar is buried in the stacked body, and extends in a stacking direction of the insulating films and the electrode films. The charge storage layer is provided between the electrode films and the semiconductor pillar. The electrode films are divided into a plurality of control gate electrodes. Each of the plurality of control gate electrodes faces the semiconductor pillar and sandwiches the charge storage layer with the semiconductor pillar.