Nonvolatile Memory Cell With Shared Diffusion Regions
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Solution Overview
Problem
Conventional nonvolatile memory devices face challenges in increasing integration density due to the complexity of forming MOS transistors and storage elements, resulting in a large footprint for memory cells.
Innovation Solution
A nonvolatile memory device is designed with a semiconductor substrate featuring first and second diffusion regions, a storage layer that can be an insulating layer or a variable resistor, and a gate structure that allows for shared diffusion regions and diode formation, enabling a more compact memory cell configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If MOS transistors and storage elements are formed using conventional methods, then reliable data storage is achieved, but the memory cell footprint becomes large, reducing integration density
Solution Approach 1:
The patent combines the storage element and transistor into a unified structure where the gate insulating layer of the transistor serves dual purposes: as the gate dielectric and as the storage layer. This merging eliminates the need for separate storage element fabrication, reducing the memory cell footprint while maintaining data storage reliability through the formation of breakdown paths in the gate insulating layer.
Solution Approach 2:
The gate insulating layer is designed to perform multiple functions: it serves as the gate dielectric for transistor operation and simultaneously as the storage medium for data retention. By applying high voltage to create breakdown paths in this single layer, the structure achieves both transistor functionality and nonvolatile memory storage without requiring additional components.
2Reliability
If the storage layer uses insulating layers requiring high voltage breakdown, then data storage capability is achieved, but the fabrication process becomes complex
Solution Approach 1:
The patent merges the storage layer formation with the transistor gate insulating layer formation into a single fabrication process. The same dielectric layer that provides gate insulation is also used as the storage medium, eliminating the need for separate storage layer deposition and patternning steps, thereby simplifying the overall fabrication process while maintaining data storage capability.
Solution Approach 2:
The gate insulating layer is formed with predetermined characteristics during the transistor fabrication process, preparing it in advance to serve as the storage layer. The layer is designed with appropriate thickness and material properties that enable subsequent breakdown path formation through high voltage application, eliminating the need for additional layer formation steps.
3Manufacturing precision
If diffusion regions are formed for each memory cell, then precise electrical control is achieved, but the area required for each cell increases
Solution Approach 1:
The patent merges diffusion regions between adjacent memory cells, allowing shared diffusion structures to serve multiple cells. This sharing of diffusion regions reduces the area required per cell while maintaining precise electrical control through the selective formation of breakdown paths in the gate insulating layer, which provides the necessary electrical isolation and control functionality.
Data Source
AI summary
The nonvolatile memory device includes a semiconductor substrate, a first and a second diffusion regions formed under a surface of the semiconductor substrate, a storage layer formed on the semiconductor substrate, a gate stacked on the storage layer, wherein the first diffusion region may at least one of active regions being separated by a part of the semiconductor substrate forming a channel region, wherein the second diffusion region may include an active region intersecting the gate insulating layer, wherein the storage layer may include an insulating layer or a variable resistor, and may service as a data storage layer to store data, and may be selected by a structure including the first and the second diffusion regions.