Nonvolatile Memory Device Skew Reduction
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Solution Overview
Problem
High-frequency operation in semiconductor memory devices is hindered by skew between output data and clock signals, leading to performance deterioration.
Innovation Solution
A nonvolatile memory device design incorporating a first and second bi-directional multiplexer, first and second registers, and I/O pads, where the frequency of the clock applied to the multiplexers is lower than that applied to the registers, reducing data transmission distance and skew by arranging registers in one-to-one relationships with I/O pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the memory device operates at high frequency, then processing speed is improved, but skew between output data and clock signal increases causing performance deterioration
Solution Approach 1:
The patent divides the data transmission path into multiple segments by introducing intermediate registers between the output circuit and final registers. This segmentation allows each segment to be optimized independently, reducing the overall skew accumulation while maintaining high-frequency operation capability
Solution Approach 2:
The patent introduces intermediate registers as mediator elements between the output circuit and final registers. These intermediary components buffer and synchronize data signals, reducing the direct skew between data and clock signals that would otherwise occur in a single-stage high-frequency path
2Reliability
If data transmission distance is reduced by arranging registers in one-to-one relationships with I/O pads, then skew is minimized, but device complexity increases
Solution Approach 1:
The patent designs bi-directional multiplexers that can operate in multiple modes (data input, data output, and skew compensation modes). This multi-functionality allows the same hardware components to serve multiple purposes, reducing the need for additional dedicated skew compensation circuits and thereby limiting the increase in device complexity
Data Source
AI summary
A nonvolatile memory device includes a first memory cell array, a first bi-directional multiplexer, a first register, a second register, a first I/O pad and a second I/O pad. The first memory cell array stores first data. The first bi-directional multiplexer receives the first data and distributes the first data into first sub-data and second sub-data. The first register stores first sub-data from the first bi-directional multiplexer. The second register stores second sub-data from a second bi-directional multiplexer. The first I/O pad outputs the first sub-data from the first register to outside. The second I/O pad outputs the second sub-data from the second register to the outside.