Non-volatile Memory Smart Erase Verify Control
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Solution Overview
Problem
In memory systems, variations among subsets of memory cells lead to differing erase speeds, causing the erase process to slow down, consume extra power, and result in over-erasure of some subsets.
Innovation Solution
The erase process is optimized by separately controlling the speed of erase for each subset of memory cells based on observed speed information, adjusting the erase speed by adding or subtracting voltage offsets to the control line for each sub-group of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a single erase signal is applied to all subsets of memory cells, then the erase process is simple to implement, but the erase speed varies among subsets causing the overall process to slow down
Solution Approach 1:
The memory cell array is divided into multiple subsets, each with its own selection gate and control lines. This segmentation allows independent control of erase operations for each subset, enabling the controller to apply different erase signals tailored to the specific erase progress of each subset, thereby resolving the contradiction between operational simplicity and erase speed.
Solution Approach 2:
The erase control system transitions from a static, uniform erase signal applied to all subsets simultaneously to a dynamic system where erase signals are adjusted in real-time based on observed erase progress. The controller monitors threshold voltage distributions and modifies erase signals dynamically for each subset, optimizing erase speed while maintaining simplicity through automated control.
2Device complexity
If a single erase signal is applied to all subsets of memory cells, then the control mechanism is simple, but power consumption increases due to extended erase duration
Solution Approach 1:
By segmenting the memory array into subsets with independent control lines, the system can apply erase signals more efficiently. Once a subset completes erasure, its control lines can be deactivated or reused, reducing the total time power is consumed and optimizing the energy efficiency of the erase operation.
Solution Approach 2:
The controller continuously monitors erase progress through threshold voltage distribution observations and maintains optimal erase signals active only when needed. This continuous adaptation ensures that power is consumed continuously and efficiently throughout the erase process, eliminating wasted energy from extended or redundant erase operations.
3Stability of the object's composition
If a single erase signal is applied to all subsets of memory cells, then the erase process is uniform, but some subsets experience over-erasure while others are under-erased
Solution Approach 1:
The system applies different erase signal characteristics to different subsets based on their specific erase progress and threshold voltage distributions. Each subset receives tailored erase control that matches its local conditions, ensuring accurate erasure without over-erasure or under-erasure, while maintaining overall uniformity through coordinated control of all subsets.
Solution Approach 2:
The controller observes threshold voltage distributions in real-time during the erase process and uses this feedback to adjust erase signals for each subset. This closed-loop feedback mechanism ensures that erase operations are precisely controlled, achieving both uniformity across all subsets and accuracy in each subset's erasure state.
Data Source
AI summary
In order to have different subsets of memory cells of a non-volatile memory system erase at the same speed, it is proposed to perform erasing by separately controlling the speed of erase for the different subsets in response to observing speed information for the subsets during the erasing.