Non-Volatile Memory Soft-Bit Restoration for Reliable Decoding
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Solution Overview
Problem
Existing memory systems face challenges in efficiently decoding and correcting data errors in non-volatile memories, particularly in multi-level cell configurations, leading to reduced data reliability and storage efficiency.
Innovation Solution
A memory system that calculates and restores soft bit data using logical sum calculations based on hard bit data and compressed soft bit data, employing an ECC circuit and SB restoration circuit to enhance error correction and data recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level cell non-volatile memories are used to increase storage density, then storage capacity is improved, but data reliability deteriorates due to increased error rates
Solution Approach 1:
The patent segments the error correction process into multiple stages: first detecting errors using hard bit data, then restoring soft bit data for more accurate decoding. This segmentation allows the system to handle the increased complexity of multi-level cell errors systematically, improving data reliability while maintaining high storage density
Solution Approach 2:
The patent performs preliminary error detection and soft bit data restoration before final decoding. By preparing and restoring soft bit data in advance, the system is better equipped to handle errors in multi-level cell memories, thereby improving reliability without sacrificing storage capacity
2Reliability
If error correction codes are applied to improve data reliability, then decoding accuracy is improved, but device complexity increases
Solution Approach 1:
The patent divides the error correction process into distinct functional blocks: hard bit data processing, soft bit data restoration, and decoding. This segmentation reduces the complexity of individual components while maintaining overall system reliability through coordinated operation of specialized modules
Solution Approach 2:
The patent introduces soft bit data as an intermediary representation between the raw multi-level cell data and the final decoded output. This intermediary layer simplifies the decoding process by providing probability information that guides error correction, reducing overall system complexity while improving reliability
3Reliability
If soft bit data restoration is implemented to improve decoding accuracy, then data reliability is improved, but processing time increases
Solution Approach 1:
The patent performs soft bit data restoration as a preliminary step before final decoding. By preparing this intermediate data in advance, the main decoding process can proceed more quickly and efficiently, reducing overall processing time while improving accuracy through the use of restored soft bit information
Solution Approach 2:
The patent applies partial error correction by first handling detectable errors using hard bit data, then selectively restoring soft bit data only when needed. This partial approach avoids the excessive processing time of complete restoration while still achieving sufficient decoding accuracy for reliable data recovery
Data Source
AI summary
According to an embodiment, a memory system comprising: a non-volatile memory including a plurality of memory cells each capable of storing at least a first bit and a second bit, and configured to calculate third soft bit data based on a logical sum calculation using at least first soft bit data corresponding to the first bit and second soft bit data corresponding to the second bit; and a memory controller configured to restore the first soft bit data and the second soft bit data based on at least first hard bit data corresponding to the first bit, second hard bit data corresponding to the second bit, and the third soft bit data.