Non-volatile Memory Step-like Channel Leakage Current
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Solution Overview
Problem
Non-volatile memory with a 2T structure experiences leakage current and program disturbance due to shortened channel length, affecting reliability and efficiency.
Innovation Solution
A non-volatile memory design with a step-like channel region formed by a trench and step-like recess, where the control gate is disposed between the trench and the recess, increasing channel length and using self-alignment to form floating and control gates, reducing manufacturing costs and time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the memory width is reduced to improve device integration, then the device size is reduced, but the channel length is shortened causing leakage current and program disturbance
Solution Approach 1:
The patent introduces a step-like recess structure that creates a three-dimensional channel region. By forming the channel with varying depths (first channel region at first depth, second channel region at second depth), the invention extends the channel length in the vertical dimension while maintaining a compact planar footprint, thus resolving the contradiction between reduced device size and maintained channel length for reliability
Solution Approach 2:
The channel region is segmented into multiple distinct regions (first channel region and second channel region) at different depths. This segmentation allows each region to contribute differently to the overall channel length, enabling extended channel length without increasing the planar device area, thereby maintaining reliability while improving integration
2Reliability
If the channel length is increased to reduce leakage current, then reliability is improved, but the device integration is reduced
Solution Approach 1:
The patent utilizes the vertical dimension by creating a step-like recess structure with channel regions at different depths. This allows the channel length to be extended vertically without increasing the horizontal device area, thus improving reliability while maintaining device integration
Solution Approach 2:
The multi-depth channel structure can be viewed as nested regions where the first channel region and second channel region are positioned at different vertical levels. This nesting approach allows extended channel length within a compact device footprint, resolving the contradiction between reliability and integration
Data Source
AI summary
A non-volatile memory is described, including a substrate, a floating gate, a control gate, a source region, and a drain region. A trench is disposed in the substrate, and a step-like recess is located in the substrate beside the trench. The floating gate is disposed on the sidewall of the trench. The control gate is disposed on the substrate between the trench and the step-like recess which extends in the step-like recess. The source region is disposed in the substrate at the bottom of the trench. The drain region is disposed in the substrate at the bottom of the step-like recess.