Non-volatile Memory Device Strapping Line Coupling Reduction
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Solution Overview
Problem
Conventional non-volatile memory devices experience a coupling effect between storage elements, leading to deteriorated performance and reliability due to threshold voltage changes affecting adjacent memory cells during programming operations.
Innovation Solution
The solution involves a non-volatile memory device architecture with a memory array comprising sub-memory arrays connected by strapping lines, where page data is programmed by simultaneously applying bit line voltages to even and odd bit lines, and using a switching block to connect data storage elements with bit lines in response to control signals, allowing for simultaneous programming of all memory cells connected to a selected word line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory cells are programmed sequentially (even pages then odd pages), then programming completeness is achieved, but coupling effect between horizontally adjacent memory cells deteriorates performance and reliability
Solution Approach 1:
The memory array is divided into first and second sub-memory arrays with interleaved even and odd bit lines. By selectively activating only the required sub-array during programming operations, the patent segments the programming process to avoid coupling effects between horizontally adjacent cells while maintaining efficient data throughput.
Solution Approach 2:
The patent implements periodic programming operations that alternate between programming even pages and odd pages in different sub-memory arrays. This periodic activation pattern ensures that when one sub-array is being programmed, the other is inactive, eliminating coupling effects while achieving complete programming of all memory cells over time.
2Manufacturing precision
If additional program operations are performed to correct threshold voltage distributions, then memory cell accuracy is improved, but programming time and complexity increase
Solution Approach 1:
The patent applies preliminary compensation voltages to bit lines before programming operations to preemptively counteract coupling effects. By preparing compensating voltages in advance based on the known programming pattern, the system eliminates threshold voltage distribution errors without requiring additional corrective programming passes.
Solution Approach 2:
The patent implements feedback mechanisms that monitor threshold voltage distributions during programming and dynamically adjust compensation voltages applied to bit lines. This real-time feedback ensures accurate threshold voltage control while maintaining efficient single-pass programming operations.
Data Source
AI summary
A non-volatile semiconductor memory device comprises first and second sub-memory arrays and a strapping line disposed between the first and second sub-memory arrays. A programming operation of the first sub-memory array is performed by simultaneously applying a programming voltage to odd and even bit lines connected to memory cells within the first sub-memory array.