Non-Volatile Memory Contact Layout via Strip Isolation

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Solution Overview

Problem

Conventional non-volatile memory manufacturing processes are complex and costly due to the need for H-shaped active regions and extensive optical proximity correction, which increases chip area and hinders miniaturization.

Innovation Solution

A manufacturing method that connects source/drain regions of adjacent active regions using contacts extending across isolation structures, reducing chip area occupancy and simplifying the process by forming strip-shaped isolation structures and using self-alignment techniques for contact formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If H-shaped active regions are formed to avoid shortage and misalignment, then manufacturing reliability is improved, but chip area increases and manufacturing complexity increases

Engineering Contradiction:
Improvemanufacturing reliabilityVSAvoidchip area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The active region is divided into two separate strip-shaped regions instead of forming a continuous H-shaped region. This segmentation allows each strip to be independently formed and aligned, eliminating the need for complex optical proximity correction while reducing the total chip area occupied by active regions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Contacts are extended in the first direction (length direction of active regions) to span across isolation structures and connect source/drain regions of adjacent active regions. This dimensional change in contact orientation allows connection without requiring additional active region area, thereby reducing chip area while maintaining reliability.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Manufacturing precision

If H-shaped active regions are formed with optical proximity correction, then manufacturing precision is improved, but manufacturing time increases

Engineering Contradiction:
Improvealignment precisionVSAvoidmanufacturing time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The active region pattern is segmented into two separate strips rather than forming a complex H-shape. This simplification of the photolithography pattern eliminates the need for extensive optical proximity correction calculations and processing, significantly reducing manufacturing time while maintaining alignment precision through simpler geometry.

Inventive Principle:
Principle #1Segmentation

3Reliability

If H-shaped active regions are formed, then contact alignment reliability is improved, but device complexity increases

Engineering Contradiction:
Improvecontact alignment reliabilityVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The active region is segmented into two simple strip shapes rather than one complex H-shape. This segmentation simplifies the overall device structure while maintaining alignment reliability through the use of extended contacts that span across isolation structures to connect the segmented regions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Contacts are extended in the first direction (parallel to active region length) rather than only in the second direction (perpendicular to active region length). This dimensional change simplifies the structural arrangement by allowing contacts to bridge across isolation structures without requiring complex H-shaped active regions, thereby reducing device complexity while maintaining alignment reliability.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS8105900B2Manufacturing method of non-volatile memory
Publication Date: 2012.01.31 NAN YA TECH
  • US8105900B2 patent drawing
  • US8105900B2 patent drawing
  • US8105900B2 patent drawing

AI summary

In a manufacturing method of a non-volatile memory, a substrate is provided, and strip-shaped isolation structures are formed in the substrate. A first memory array including memory cell columns is formed on the substrate. Each memory cell column includes memory cells connected in series with one another, a source/drain region disposed in the substrate outside the memory cells, select transistors disposed between the source/drain region and the memory cells, control gate lines extending across the memory cell columns and in a second direction, and first select gate lines respectively connecting the select transistors in the second direction in series. First contacts are formed on the substrate at a side of the first memory array and arranged along the second direction. Each first contact connects the source/drain regions in every two adjacent active regions.