Non-volatile Memory Sub-block Programming Order Optimization
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Solution Overview
Problem
Non-volatile memory systems face inefficiencies in programming and erasing processes due to variations in sub-block erase speeds, leading to prolonged operation times and potential data disturb issues.
Innovation Solution
A method where sub-blocks are programmed and erased in an optimized order from slowest to fastest, with concurrent programming across multiple planes using the completion of the fastest plane as a trigger to test for program failure, allowing for early abortion of failed sub-blocks and reducing overall processing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sub-blocks are programmed and erased in conventional order, then processing continues uniformly across all sub-blocks, but overall operation time is prolonged due to variations in sub-block erase speeds
Solution Approach 1:
The system performs preliminary identification of sub-block erase speeds and establishes an optimized processing order before executing programming and erasing operations. By determining which sub-blocks are slower or faster erasers in advance, the system can schedule operations to prevent idle waiting time, thereby reducing overall operation completion time while maintaining high productivity.
Solution Approach 2:
The system dynamically adjusts the programming and erasing sequence based on measured sub-block performance characteristics. Instead of a static uniform processing order, the system adapts the operation sequence to match actual sub-block speeds, allowing faster sub-blocks to be processed earlier and slower sub-blocks to be processed later, thus optimizing total operation time without sacrificing throughput.
2Reliability
If all sub-blocks are processed completely before checking for failures, then thorough verification is achieved, but data disturb risks increase and time is wasted on failed sub-blocks
Solution Approach 1:
The system implements feedback mechanisms by periodically verifying programming results during the erasing process rather than waiting for completion. When a sub-block fails verification, the system receives feedback and immediately aborts further processing of that sub-block. This early detection prevents data disturb risks associated with continuing operations on failed sub-blocks while maintaining reliable failure detection.
Solution Approach 2:
The system rushes through the verification process at critical checkpoints during erasing operations. By performing quick verification checks at strategically chosen points rather than waiting for complete processing, the system can identify and skip failed sub-blocks early, preventing the propagation of errors and reducing data disturb risks while maintaining adequate verification thoroughness.
3Productivity
If conventional programming sequences are used across multiple planes, then all planes are programmed uniformly, but overall processing time increases due to lack of optimization
Solution Approach 1:
The system segments the multi-plane programming process into independent parallel operations. Each plane is programmed concurrently using dedicated resource allocations, and the system tracks completion status of each plane individually. This segmentation allows the fastest plane completion to trigger early verification and abort procedures, reducing total multi-plane operation time while maintaining high programming efficiency across all planes.
Data Source
AI summary
A non-volatile memory system separately performs a memory operation for multiple sub-blocks of a block in order from previously determined slowest sub-block of the block to a previously determined faster sub-block of the block. As a slower sub-block is more likely to fail, this order of is more likely to identify a failure earlier in the process thereby saving time and reducing potential for a disturb. In some embodiments, the proposed order of operation can be used in conjunction with a programming process that concurrently programs blocks in multiple planes using completion of programming of a fastest plane to a data state as a trigger to test for program failure of other planes to the data state.