Non-Volatile Memory Sub-Block Programming and Partial Erase
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Solution Overview
Problem
Conventional NAND flash memory devices face challenges in programming and erasing operations, particularly in maintaining threshold voltage distributions and avoiding over-erase conditions due to sequential programming, which can lead to reliability issues, especially in multi-level cell devices.
Innovation Solution
The method involves programming a first sub-block of a memory block and determining when a reference word line is programmed, followed by partial erasing of a second sub-block using distinct erase voltages, which helps in maintaining the threshold voltage distribution and preventing over-erase conditions by resetting the voltage distributions of erased cells before further programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential programming of word lines is performed from first to last, then programming completeness is achieved, but threshold voltage distribution deteriorates and over-erase conditions occur
Solution Approach 1:
The memory block is divided into multiple sub-blocks, and programming is performed in a predetermined order through these sub-blocks rather than sequentially through all word lines. This segmentation allows intermediate erase operations to be performed on already-programmed sub-blocks, maintaining voltage distribution while continuing programming in other sub-blocks.
Solution Approach 2:
Erase operations are performed preliminarily on sub-blocks that have completed programming, before the entire programming process is finished. This preliminary erasing maintains the threshold voltage distribution window by resetting voltage levels in completed sub-blocks while other sub-blocks are still being programmed.
2Reliability
If entire memory block is erased prior to programming, then data integrity is ensured, but programming time increases due to full erase requirement
Solution Approach 1:
Instead of erasing the entire memory block before programming, the block is divided into sub-blocks that are erased individually as they complete programming. This eliminates the need for a preliminary full-block erase operation, significantly reducing the total time required while maintaining data integrity through selective erasing.
Solution Approach 2:
Only the necessary portions of the memory block are erased at any given time - specifically, sub-blocks that have completed programming are erased, while other sub-blocks remain untouched during intermediate stages. This partial erasing approach avoids the time penalty of full-block erase while ensuring data integrity in programmed regions.
3Quantity of substance
If multi-level cell storage is implemented, then storage capacity increases, but threshold voltage distribution control becomes more difficult
Solution Approach 1:
The programming process is segmented into multiple sub-blocks with controlled progression, allowing precise management of threshold voltage distributions across multi-level cells. By processing sub-blocks in a predetermined order and performing intermediate erases, the voltage distribution window is maintained even as storage capacity increases through MLC implementation.
Data Source
AI summary
A method is for programming a memory block of a non-volatile memory device. The non-volatile memory device is operatively connected to a memory controller, and the memory block defined by a plurality of word lines located between a string select line and a common source line corresponding to the string select line. The method includes programming a first sub-block of the memory block, determining in the non-volatile memory device when a reference word line is programmed during programming of the first sub-block, and partial erasing a second sub-block of the memory block upon determining that the reference word line is programmed during programming of the first sub-block.