Non-volatile Memory Sub-gate Structure for Charge Suppression
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Solution Overview
Problem
Non-volatile memory devices, particularly flash memory devices, face challenges in data retention and program-erase cycling characteristics due to charge accumulation between memory cells, which deteriorates with downscaling and multi-level programming, leading to potential read errors and reduced reliability.
Innovation Solution
Incorporating sub-gates between control gates in the non-volatile memory device structure, where the sub-gates are electrically floated or apply an inhibit voltage opposite to the program voltage during programming, to suppress the fringing field and prevent charge accumulation in inter-memory cell regions, thereby enhancing data retention and program-erase cycling characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are downscaled to increase integration and capacity, then device density and storage capacity are improved, but data retention performance deteriorates due to charge spread toward adjacent memory cells
Solution Approach 1:
The control gate structure is segmented by introducing sub-gates between adjacent control gates. This segmentation creates electrical isolation regions that prevent charge spread between memory cells, thereby maintaining data retention performance while enabling continued downscaling for increased storage capacity.
Solution Approach 2:
Sub-gates are introduced as intermediary elements between adjacent control gates. These sub-gates act as mediators that block the fringing electric fields and prevent charge migration between neighboring memory cells, resolving the charge spread issue caused by downsaling.
2Quantity of substance
If multi-level programming is implemented to increase storage capacity, then device capacity is improved, but program-erase cycling characteristics deteriorate due to charge accumulation in inter-memory cell regions
Solution Approach 1:
The control gate is divided into multiple segments with sub-gates positioned between them. This segmentation prevents charge accumulation in inter-memory cell regions during multi-level programming operations, thereby maintaining reliable program-erase cycling characteristics while enabling increased storage capacity.
Solution Approach 2:
Sub-gates serve as intermediary structures that block charge migration paths during programming and erasing operations. This intermediary structure prevents charge accumulation in forbidden regions, ensuring stable program-erase cycling behavior even when implementing multi-level cell programming for increased capacity.
3Reliability
If sub-gates are added between control gates to suppress fringing field, then data retention is improved, but device complexity increases
Solution Approach 1:
The sub-gates are formed using the same conductive material and fabrication processes as the control gates, merging the manufacturing steps. This approach improves data retention by suppressing fringing fields while minimizing the increase in device complexity through process integration.
Solution Approach 2:
The width of sub-gates is optimized within a specific ratio range (0.1 to 1 relative to the distance to adjacent control gates) to achieve effective fringing field suppression with minimal impact on device complexity. This parameter optimization balances performance improvement with structural simplicity.
4Reliability
If sub-gates are introduced to prevent charge accumulation, then program-erase cycling characteristics are improved, but manufacturing complexity increases
Solution Approach 1:
The sub-gate formation is merged with the existing control gate fabrication process, using the same conductive material deposition and patterning steps. This approach improves program-erase cycling characteristics while avoiding significant increases in manufacturing complexity through process integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively minimizes charge accumulation between memory cells, improving data retention and program-erase cycling performance, ensuring reliable operation and reducing the risk of read errors in downscaled and multi-level memory devices.
Implementation Method 1
suppress the fringing field and prevent charge accumulation in inter-memory cell regions
Data Source
AI summary
Provided are a non-volatile memory device and a method of fabricating the same. The non-volatile memory includes a channel layer; a data storage layer disposed on the channel layer; a plurality of control gates arranged on the data storage layer and spaced apart from one another; and one or more sub-gates, at least one of the sub-gates being arranged between two adjacent control gates.