Non-volatile Memory Cell Array with Parallel Switching for Read Accuracy
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Solution Overview
Problem
As semiconductor memory devices increase in capacity, the size of memory cells decreases, leading to reduced active width and capacitance, which deteriorates programming and erasing efficiency, making it difficult to determine on-cell and off-cell states, resulting in read errors.
Innovation Solution
A non-volatile memory device with a memory cell block, first and second switching blocks, where multiple memory cells are connected through switching devices in parallel, enhancing current driving capability and reducing read errors by improving on-cell current characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory capacity is increased by reducing memory cell size, then storage density is improved, but on-cell current decreases making read determination difficult
Solution Approach 1:
The bit line is divided into multiple local bit lines (BL1-BL4) that are selectively connected to the memory cell array through switching devices. This segmentation allows the on-cell current to be concentrated and transmitted through dedicated local bit lines, improving read accuracy despite reduced cell size
Solution Approach 2:
Switching devices (T31-T34) are introduced as intermediary elements between the global bit lines and local bit lines. These switching devices selectively connect specific local bit lines to the memory cell array, enabling precise control and enhancement of on-cell current transmission to improve read determination reliability
2Quantity of substance
If memory cell size is reduced to increase capacity, then storage density improves, but programming and erasing efficiency deteriorates
Solution Approach 1:
The memory cell array is divided into multiple blocks (MCB1-MCB4) that can be independently accessed and operated. This block segmentation allows programming and erasing operations to be performed on specific blocks without affecting the entire array, maintaining efficiency despite reduced individual cell size
Solution Approach 2:
The switching devices provide dynamic control over which local bit lines are connected to which memory blocks. This dynamic connectivity allows flexible configuration of read and write operations, enabling efficient access patterns that compensate for reduced cell dimensions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances read speed and reduces read errors by improving the on-cell current characteristics, ensuring accurate determination of on-cell and off-cell states.
Implementation Method 1
programming and erasing is performed using an FN tunneling method
Data Source
AI summary
A non-volatile memory device includes a memory cell block, a first switching block, and a second switching block. A plurality of memory cells are arranged in the memory cell block and each of the memory cells includes a memory transistor having a floating gate and a control gate and is connected to a local bit line and includes a selection transistor connected to the memory transistor in series that is connected to a source line. The first switching block selectively connects a global bit line to the local bit line and the second switching block controls the memory cells in the memory cell block in units of a predetermined number of bits. The first switching block includes at least two switching devices connected in parallel between the global bit line and the local bit line.