Deep Learning Classifiers With Non-Volatile Memory Synapses
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Solution Overview
Problem
The development of high-performance artificial neural networks is hindered by a lack of adequate hardware technology, particularly in terms of high connectivity and energy efficiency, as existing CMOS-implemented synapses are bulky and digital supercomputers or specialized graphics processing units suffer from high cost and mediocre energy efficiency compared to biological networks.
Innovation Solution
The use of non-volatile memory arrays as synapses in artificial neural networks, where each memory cell stores a weight value corresponding to the number of electrons on a floating gate, allowing for precise tuning and continuous programming of synapse weights, enabling efficient and fine-tuning adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If CMOS analog circuits are used for synapses to achieve high connectivity, then computational parallelism is improved, but the device area becomes too bulky
Solution Approach 1:
The patent replaces bulky CMOS analog circuits with non-volatile memory cells (such as floating gate, charge trap, or magnetic tunnel junction cells) to implement synapses. This substitution maintains the ability to store weight values and perform multiply-accumulate operations while dramatically reducing the area per synapse. The memory cells naturally provide non-volatile storage and analog weight representation without requiring the complex CMOS transistor networks needed for traditional analog synapses.
Solution Approach 2:
The patent changes the fundamental parameter of synapse implementation from active CMOS circuits to passive memory cell structures. By utilizing the inherent electrical characteristics of memory cells (such as conductance states in floating gate or magnetoresistive cells), the system achieves synapse functionality with much smaller footprint. The weight values are encoded as continuous parameters in the memory cells, enabling analog computation without requiring bulky active circuitry.
2Productivity
If digital supercomputers or specialized graphics processing units are used to achieve high connectivity, then computational capability is improved, but energy efficiency deteriorates
Solution Approach 1:
The patent substitutes digital computational systems (supercomputers or GPUs) with an analog computing system based on non-volatile memory arrays. The key energy efficiency gain comes from performing multiply-accumulate operations directly in the memory array using Ohm's law and Kirchhoff's current law, eliminating the need to move data between memory and processing units. This in-memory computing approach dramatically reduces energy consumption compared to digital systems that require continuous data transfer and processing cycles.
Solution Approach 2:
The memory array performs computational operations autonomously without requiring external processing units. When input voltages are applied to the memory array, the stored weight values automatically perform multiplication through conductance modulation, and summation occurs naturally through parallel current paths. This self-service computational capability eliminates the energy overhead of data movement and external processing, achieving high energy efficiency.
3Area of stationary object
If non-volatile memory arrays are used as synapses to reduce device area, then area efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs feedback mechanisms during the programming process to achieve precise weight values. After programming a weight value into a memory cell, the system reads back the actual value and compares it with the target value. If discrepancies exceed a threshold, additional programming pulses are applied to correct the error. This feedback-based calibration process compensates for manufacturing variations and ensures high precision weight values despite process tolerances in memory cell fabrication.
Solution Approach 2:
The patent performs preliminary characterization and calibration of memory cells during or after fabrication to establish accurate weight values. By pre-programming reference weights and characterizing the actual values achieved, the system creates lookup tables or calibration data that compensate for manufacturing variations. This preliminary action ensures that subsequent computations use accurate weight values without requiring extremely tight manufacturing tolerances.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides a power-efficient hardware solution for neural networks, reducing the need for separate multiplication logic circuits and allowing for precise tuning of synapse weights, enhancing computational parallelism and energy efficiency.
Implementation Method 1
each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region
Data Source
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AI summary
An artificial neural network device that utilizes one or more non-volatile memory arrays as the synapses. The synapses are configured to receive inputs and to generate therefrom outputs. Neurons are configured to receive the outputs. The synapses include a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells are configured to multiply the inputs by the stored weight values to generate the outputs.