Nonvolatile Memory System Block Allocation for Parallel CPU Access

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Solution Overview

Problem

In memory systems like solid state drives, the allocation of system blocks leads to performance issues due to simultaneous access by multiple CPUs, resulting in serial access to shared channels, which decreases efficiency.

Innovation Solution

A method is implemented where system blocks dedicated to specific CPUs are allocated to separate channels, allowing parallel operations by ensuring each CPU's dedicated blocks are accessed on distinct channels, and common use blocks are distributed to balance usable blocks across planes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If system blocks are shared among multiple CPUs, then device complexity is reduced, but access speed decreases due to serial access requirements

Engineering Contradiction:
Improvesystem block allocation complexityVSAvoidsystem data access speed
Core Design Contradiction:
Device complexityVSSpeed

Solution Approach 1:

The patent divides system blocks into separate dedicated blocks for each CPU (e.g., CPU0 system block, CPU1 system block) and allocates them to different channels. This segmentation allows each CPU to access its dedicated system block independently through its own channel, eliminating serial access conflicts and improving access speed while maintaining manageable complexity through systematic allocation

Inventive Principle:
Principle #1Segmentation

2Speed

If dedicated system blocks are allocated to each CPU on separate channels, then access speed improves, but device complexity increases

Engineering Contradiction:
Improvesystem data access speedVSAvoidsystem block allocation complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent applies local quality by allocating specific system blocks to specific CPUs based on their dedicated channel assignments. Each CPU has its own dedicated system block(s) that it can access without interference from other CPUs. This localized allocation strategy improves access speed for each CPU while the overall complexity is managed through systematic allocation rules rather than random distribution

Inventive Principle:
Principle #3Local quality

3Device complexity

If common use blocks are concentrated in one location, then device complexity is reduced, but productivity decreases due to access bottlenecks

Engineering Contradiction:
Improveblock allocation managementVSAvoidsystem operation efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent segments common use blocks and distributes them across different planes and channels rather than concentrating them in one location. This distribution allows multiple CPUs to access different common use blocks simultaneously through different channels, eliminating access bottlenecks and improving overall system productivity while maintaining manageable complexity through systematic distribution

Inventive Principle:
Principle #1Segmentation

4Device complexity

If blocks are accessed serially through shared channels, then device complexity is reduced, but loss of time increases

Engineering Contradiction:
Improvechannel allocation simplicityVSAvoidsystem data access time
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The patent introduces a new dimension to the access architecture by allocating different channels (spatial dimension) to different CPUs for accessing their dedicated system blocks. This dimensional expansion transforms the access pattern from serial (one-dimensional time-based) to parallel (multi-dimensional space-based), significantly reducing access time while keeping channel allocation management relatively simple through systematic assignment

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS9952967B2Method for controlling nonvolatile memory and storage medium storing program
Publication Date: 2018.04.24 KIOXIA CORP
  • US9952967B2 patent drawing
  • US9952967B2 patent drawing
  • US9952967B2 patent drawing

AI summary

According to one embodiment, a method for controlling a nonvolatile memory includes allocating a first system block to a physical block included in one of the first and second parallel operation elements. The first system block is used by a first CPU controlling the nonvolatile memory but is not used by a second CPU controlling the nonvolatile memory. The method includes allocating a second system block to a physical block included in the other of the first and second parallel operation elements. The second system block is used by the second CPU but is not used by the first CPU.