Nonvolatile Memory Electrodes With Tapered Walls

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Solution Overview

Problem

Cross-point nonvolatile memory devices face limitations in bit density improvement due to weakened adhesion between finer interconnects and the substrate, leading to reduced reliability.

Innovation Solution

The design includes lower and upper side electrodes with forward-tapered and reverse-tapered side walls, respectively, separated by insulating layers, allowing for a higher bit density configuration without compromising adhesion and reliability, achieved through a manufacturing process involving the formation of electrodes with insulating spacer layers and conductor filling between them.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the bit density is increased by making interconnects finer, then the bit density improves, but the adhesion between interconnects and substrate weakens

Engineering Contradiction:
Improvebit densityVSAvoidadhesion
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent transitions from planar 2D interconnect layout to a 3D structure by forming electrodes with tapered side walls that extend vertically. The first electrode has a forward taper and the second electrode has a reverse taper, creating an interdigitated three-dimensional configuration that increases contact surface area and improves adhesion while maintaining high bit density.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent changes the geometric parameters of the electrodes by forming tapered side walls with specific angles. The forward-tapered first electrode and reverse-tapered second electrode create optimized contact surfaces that enhance adhesion strength. This parameter change allows finer interconnects to maintain reliable adhesion despite reduced dimensions.

Inventive Principle:
Principle #35Parameter changes

2Quantity of substance

If the interconnect width is reduced to increase bit density, then the bit density improves, but the reliability decreases

Engineering Contradiction:
Improvebit densityVSAvoidinterconnect reliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent moves from two-dimensional planar interconnects to three-dimensional tapered structures. The vertical extension and interdigitated arrangement of the first and second electrodes with opposite tapers create additional contact area and structural integrity, compensating for the reduced horizontal dimensions and maintaining reliability at higher density.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent employs a composite structure combining insulating layers with tapered conductive electrodes. The insulating layer separates the first and second electrodes while the tapered conductive portions provide enhanced mechanical and electrical reliability. This composite approach allows finer interconnects to maintain structural soundness and operational reliability.

Inventive Principle:
Principle #40Composite materials

Data Source

PatentUS8258494B2Nonvolatile memory device and method for manufacturing same
Publication Date: 2012.09.04 KIOXIA CORP
  • US8258494B2 patent drawing
  • US8258494B2 patent drawing
  • US8258494B2 patent drawing

AI summary

A nonvolatile memory device, includes: a lower side electrode aligned in a first direction; an upper side electrode positioned above the lower side electrode and aligned in a second direction intersecting the first direction; and a memory unit provided between the lower side electrode and the upper side electrode. At least one selected from the lower side electrode and the upper side electrode includes a first electrode and a second electrode, the first electrode having a forward-tapered side wall, the second electrode having a reverse-tapered side wall and being adjacent to the first electrode via an insulating layer in substantially identical plane.