Non-Volatile Memory Threshold Control to Reduce Charge Recombination
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Solution Overview
Problem
Existing non-volatile semiconductor memory devices face challenges in maintaining data integrity and reducing data loss due to charge recombination between adjacent memory transistors, especially in three-dimensionally arranged memory cells, which can lead to increased delay times when performing write operations.
Innovation Solution
The implementation of a control circuit that performs an erase operation to set a first threshold voltage level, followed by a series of first write operations to establish a higher second threshold voltage level, allowing for the execution of other functions during these write operations, including read and second write operations, thereby reducing charge recombination and enhancing data reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensionally arranged memory cells are used to achieve higher integration, then memory density is improved, but charge recombination between adjacent memory transistors increases causing data loss
Solution Approach 1:
The memory cell array is divided into multiple blocks, with each block containing a set of memory cells connected to common word lines. This segmentation isolates charge accumulation regions, preventing charge recombination between adjacent memory transistors while maintaining high integration density through three-dimensional stacking.
Solution Approach 2:
An erase operation is performed as an intermediary step before write operations. This erase operation clears residual charges from the charge accumulation layer, eliminating charge recombination effects from previously erased or written data, thereby ensuring data integrity in high-density three-dimensional memory structures.
2Reliability
If multiple write operations are performed to establish threshold voltage levels, then data reliability is improved, but operation time increases
Solution Approach 1:
An erase operation is performed preliminarily before write operations to establish a known initial state (first threshold voltage level). This preliminary action ensures that subsequent write operations start from a consistent baseline, improving data reliability while allowing interrupt operations to be efficiently scheduled during the write process.
Solution Approach 2:
The control circuit dynamically manages multiple operations including erase, write, and interrupt operations. By allowing read and second write operations to interrupt first write operations, the system optimizes operation time while maintaining data reliability through proper threshold voltage level establishment.
3Productivity
If interrupt operations are allowed during write operations, then productivity is improved, but operation complexity increases
Solution Approach 1:
The control circuit is designed with multi-functionality to handle erase operations, write operations, read operations, and interrupt operations within a unified architecture. This universal design allows different operation types to be managed through common control logic, improving productivity while controlling complexity through standardized operation handling.
Solution Approach 2:
The system allows read and second write operations to interrupt first write operations, ensuring that the memory device remains productive throughout the operation sequence. This continuous useful action maximizes throughput by eliminating idle time while the control circuit manages operation transitions through standardized protocols.
Data Source
AI summary
A non-volatile semiconductor memory device includes a memory cell array and a control circuit. A control circuit performs an erase operation providing a memory cell with a first threshold voltage level for erasing data of a memory cell, and then perform a plurality of first write operations providing a memory cell with a second threshold voltage level, the second threshold voltage level being higher than the first threshold voltage level and being positive level. When the control circuit receives a first execution instruction from outside during the first write operations, the first execution instruction being for performing first function operation except for the erase operation and the first write operations, the circuit performs the first function operation during the first write operations.