Nonvolatile Memory Read Voltage Adjustment via Time-Read Level Look-Up Table

The patent implements dynamic read voltage adjustment by introducing a time-read level look-up table that stores read level shift values corresponding to different program elapsed times. The memory controller dynamically selects and applies the appropriate read level shift based on the stored program time, enabling the read voltage to adapt to temporal changes in memory characteristics without requiring complex real-time analysis.

The patent changes the read voltage parameter based on multiple factors including temperature, program elapsed time, and memory cell deterioration. By storing read level shift values in a look-up table and adjusting the read voltage according to these pre-calibrated values, the system maintains data retention reliability under varying conditions without implementing complex real-time control algorithms.

The patent performs preliminary characterization of memory cell behavior under different temperatures and program elapsed times, storing the read level shift values in a look-up table before normal operation. This pre-characterization approach eliminates the need for complex real-time measurements during read operations, as the system simply retrieves pre-determined correction values based on temperature and time parameters.

The patent implements a feedback mechanism where the memory controller monitors read operation results and adjusts the read level shift values in the look-up table based on detected errors or performance degradation. This feedback loop ensures that the measurement precision requirements are maintained while continuously improving data retention reliability under varying operating conditions.

The patent performs the computationally intensive valley search operation periodically or at predetermined intervals rather than for every read operation. The look-up table is updated at these periodic intervals to reflect current memory characteristics, while normal read operations simply retrieve pre-calculated values. This approach maintains high read operation accuracy while minimizing the time penalty associated with valley search operations.

The patent applies partial valley search by performing the operation on selected memory blocks or pages rather than the entire memory array. This selective approach maintains read operation accuracy for critical data while reducing the overall time consumption by limiting the scope of valley search operations to only those areas where it is most beneficial.