Nonvolatile Memory Transistor Floating Gate Capacitance
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Solution Overview
Problem
In flash memory cells, increasing the capacitance between the floating gate and the control gate is challenging, especially when the floating gate thickness is small, which hinders effective writing and erasing of data.
Innovation Solution
A nonvolatile semiconductor memory transistor design featuring an island-shaped semiconductor with a floating gate surrounding the channel region and a control gate surrounding the floating gate, utilizing tunnel and inter-polysilicon insulating films to enhance capacitance, along with a control gate line electrically connected to the control gate, allowing the floating gate to extend below and above the control gate and control gate line, thereby increasing electrostatic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the floating gate thickness is increased to increase capacitance between floating gate and control gate, then the capacitance increases, but the device structure becomes more complex and manufacturing becomes more difficult
Solution Approach 1:
The patent implements a surrounding gate structure where the control gate wraps around the floating gate in three dimensions, creating a nested configuration. This allows the control gate to contact the floating gate at multiple locations (top, bottom, and side surfaces), effectively increasing capacitance without requiring increased floating gate thickness. The nested arrangement maximizes the overlapping area between gates while maintaining a compact structure.
Solution Approach 2:
The patent transitions from a planar gate configuration to a three-dimensional surrounding gate structure. The control gate extends around the floating gate in multiple spatial dimensions, creating capacitive coupling surfaces at the top, bottom, and lateral surfaces of the floating gate. This dimensional expansion increases total capacitance without increasing the floating gate thickness.
2Productivity
If the floating gate thickness is increased to facilitate writing and erasing operations, then writing and erasing efficiency improves, but the manufacturing precision requirements increase
Solution Approach 1:
The surrounding gate structure nests the control gate around the floating gate, creating multiple capacitive coupling interfaces. This configuration enhances the electric field coupling between gates, improving electron injection and extraction efficiency during write and erase operations without requiring thicker floating gates, thereby avoiding stringent thickness control requirements.
Solution Approach 2:
Instead of changing the floating gate thickness parameter, the patent changes the geometric configuration parameter by implementing a three-dimensional surrounding gate structure. This parameter change achieves enhanced capacitive coupling and improved write/erase efficiency while maintaining the floating gate at optimal thin thickness, avoiding manufacturing precision issues associated with thick floating gates.
3Reliability
If a surrounding gate structure is implemented to increase capacitance, then capacitive coupling improves, but the device complexity increases
Solution Approach 1:
The control gate is configured to surround the floating gate in a nested arrangement, creating capacitive coupling at multiple surfaces (top, bottom, and sides). This nested structure maximizes capacitance enhancement while maintaining a systematic and manufacturable configuration that does not excessively increase device complexity.
Solution Approach 2:
The surrounding gate structure serves multiple functions simultaneously: it increases capacitance through extended coupling area, provides electrical control over the floating gate, and maintains compatibility with existing manufacturing processes. This multi-functionality achieves high capacitive coupling without proportionally increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively increases the capacitance between the floating gate and the control gate, facilitating improved writing and erasing operations in flash memory cells by enhancing the capacitive coupling, thus improving data storage efficiency.
Implementation Method 1
a tunnel insulating film is interposed between the floating gate and the channel region
Implementation Method 2
an inter-polysilicon insulating film is interposed between the control gate and the floating gate
Data Source
AI summary
A nonvolatile semiconductor memory transistor includes an island-shaped semiconductor having a source region, a channel region, and a drain region formed in this order from the Si substrate side, a floating gate surrounding the outer periphery of the channel region with a tunnel insulating film interposed therebetween, a control gate surrounding the outer periphery of the floating gate with an inter-polysilicon insulating film interposed therebetween, and a control gate line connected to the control gate and extending in a predetermined direction. The floating gate extends to regions below and above the control gate and to a region below the control gate line. The inter-polysilicon insulating film is interposed between the floating gate and the upper surface, lower surface, and inner side surface of the control gate and between the control gate line and a portion of the floating gate that extends to the region below the control gate line.