Non-volatile Memory Transistor Grouping for High Voltage Reliability
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Solution Overview
Problem
The reduction in size of access and control gate selection transistors in non-volatile memory devices leads to voltage limitations, causing breakdowns and premature wear, while existing solutions like split voltage techniques require significant surface area, making them unsuitable for compact memory designs.
Innovation Solution
The proposed solution involves grouping control gate selection transistors in semiconductor recesses, allowing for the application of high erasure and programming voltages without exceeding breakdown voltages, using an alternation of recesses for even and odd pages, and applying compensation voltages to prevent junction breakdowns, thereby reducing surface area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of access transistors and control gate selection transistors is reduced to increase memory density, then memory capacity is improved, but the transistors can no longer transmit the high voltages required for writing data due to breakdown voltage limits
Solution Approach 1:
The invention divides the memory structure into multiple recesses, each containing memory words and their associated control gate selection transistors. This segmentation allows high voltages to be applied locally to selected memory words without requiring all transistors in the entire memory array to withstand the full voltage, thus enabling high-voltage operation in compact transistors.
Solution Approach 2:
The invention applies high voltages locally to specific recesses containing memory words that need writing or erasing, rather than applying high voltage across the entire memory array. This local application of high voltage allows compact transistors to operate at high voltages only when needed, without requiring all transistors to have high breakdown voltages.
2Reliability
If split voltage technology is used to apply high voltages without exceeding breakdown voltages, then data writing capability is improved, but significant surface area is required at the periphery for charge pumps
Solution Approach 1:
The invention nests the control gate selection transistors within the same recesses as the memory words they control, rather than placing them in separate peripheral areas. This nesting eliminates the need for separate charge pump circuits at the periphery, as the high voltage can be applied directly to the recesses containing both the memory words and their control transistors.
Solution Approach 2:
The invention moves the control gate selection transistors from a peripheral two-dimensional layout to a three-dimensional structure where they are integrated within the recesses housing the memory words. This vertical integration reduces the peripheral surface area required for voltage generation circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the efficient application of high voltages necessary for data writing without transistor breakdown, while minimizing the surface area required, making it compatible with compact memory designs and maintaining data retention performance.
Implementation Method 1
The voltages implemented in the course of data writes, generally including an erasure cycle and a programming cycle, must be high enough to inject or extract a charge of the floating gate of the state transistors through the Fowler-Nordheim effect.
Data Source
AI summary
A memory device includes a memory plane including a succession of neighboring semiconductor recesses of a first type of conductivity, wherein each semiconductor recess houses a plurality of memory words including a plurality of memory cells, wherein each memory cell includes a state transistor having a floating gate and a control gate. The memory device further includes a plurality of control gate selection transistors respectively allocated to each memory word of the plurality of memory words, wherein each control gate selection transistor is coupled to the control gates of the state transistors of the memory word to which the control gate selection transistor is allocated, wherein each control gate selection transistor is situated in and on a neighbor semiconductor recess of the semiconductor recess housing the memory word to which the control gate selection transistor is allocated.