Non-volatile Memory Floating Gate Trench Isolation
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Solution Overview
Problem
The integration of semiconductor devices leads to increased parasitic capacitance between adjacent cells in non-volatile memory devices, causing interference and deterioration of device characteristics due to the large contact area between floating gates and dielectric layers.
Innovation Solution
The solution involves forming trenches in the substrate between stacked patterns, gap-filling these trenches with an isolation layer to align the surfaces of floating gates and dielectric layers, and reducing the thickness of the floating gate to minimize parasitic capacitance, while using a high dielectric constant insulation layer to compensate for the reduced coupling ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the dielectric layer is formed along the surface of the floating gate protruding from the isolation layer to secure proper coupling ratio, then the coupling ratio is improved, but parasitic capacitance between adjacent cells increases causing interference and deterioration of device characteristics
Solution Approach 1:
The patent extracts the problematic protruding portion of the floating gate by forming a trench that removes the excess floating gate material. This eliminates the source of parasitic capacitance while preserving the necessary coupling between the control gate and floating gate through the remaining structure.
Solution Approach 2:
The patent segments the floating gate structure by forming a trench that divides it into distinct regions. The floating gate is separated into portions within the trench and portions on the surface, with the isolation layer filling the trench space. This segmentation reduces the contact area between adjacent floating gates and dielectric layers, thereby reducing parasitic capacitance.
2Productivity
If the integration degree of semiconductor device is increased, then productivity is improved, but the gap between adjacent cells becomes narrower causing increased parasitic capacitance and interference
Solution Approach 1:
The patent introduces a vertical dimension by forming trenches that extend into the substrate. This vertical segmentation allows for higher horizontal integration density while maintaining electrical isolation between adjacent cells through the trench structure filled with isolation layer, thus reducing parasitic capacitance even as integration degree increases.
3Object-generated harmful factors
If the surface of floating gate is aligned with the surface of isolation layer by gap-filling trenches, then parasitic capacitance is reduced, but the process complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming the trench and filling it with isolation layer before finalizing the dielectric layer formation. This preliminary structuring establishes the proper surface alignment between floating gate and isolation layer, simplifying subsequent processing steps and reducing overall process complexity despite the additional trench formation step.
Data Source
AI summary
A non-volatile memory device includes a plurality of stacked patterns where a tunnel insulation layer, a floating gate, and a dielectric layer are sequentially stacked over a substrate, trenches formed in the substrate between the stacked patterns, an isolation layer gap-filling the trenches and space between the stacked patterns, and a control gate formed over the dielectric layer.