Nonvolatile Memory Trench Transistor Charge Trapping
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Solution Overview
Problem
Conventional DRAM memory requires frequent data refreshing due to volatility, leading to high power consumption and limited memory capacity in small-sized devices, as it relies on charging and non-charging capacitors to store binary data.
Innovation Solution
A non-volatile memory design incorporating a charge-trapping layer within the DRAM structure, utilizing a SONOS device with trench transistors to replace the storage node, allowing for digital data storage based on capacitance changes, and eliminating the need for refreshing, thus reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional DRAM structure with capacitor is used, then fast access function is achieved, but data must be regularly refreshed consuming power
Solution Approach 1:
The patent changes the fundamental parameter of data storage from volatile capacitor charging/discharging to non-volatile charge trapping in the charge-trapping layer. This parameter change eliminates the need for periodic refreshing while maintaining fast access characteristics, thereby reducing power consumption.
Solution Approach 2:
The patent employs a composite structure combining silicon oxide tunneling layer, silicon nitride charge-trapping layer, and silicon oxide blocking layer (SONOS structure). This composite material system enables both fast write access (through tunneling) and non-volatile storage (through charge trapping), resolving the contradiction between speed and power consumption.
2Length of moving object
If memory cell size is reduced to minimize device size, then device dimension is minimized, but manufacturing precision and integrity become more difficult to maintain
Solution Approach 1:
The patent transitions from planar capacitor-based storage to vertical trench transistor structure with stacked dielectric layers. This dimensional change allows scaling of storage capacity in the vertical direction rather than reducing lateral dimensions, thereby maintaining manufacturing precision while minimizing overall device footprint.
Solution Approach 2:
The patent implements a nested structure where the charge-trapping layer is embedded within the trench transistor gate stack. The SONOS structure (silicon oxide/silicon nitride/silicon oxide layers) is nested within the trench, allowing high-density storage without increasing lateral device dimensions or compromising manufacturing integrity.
3Reliability
If charge-trapping layer is added to create non-volatile memory, then data retention without power is achieved, but device structure becomes more complex
Solution Approach 1:
The patent designs the trench transistor with charge-trapping layer to serve multiple functions: the tunneling dielectric enables charge injection, the charge-trapping layer stores data non-volatily, and the blocking dielectric prevents charge loss. This multi-functional structure achieves reliable data retention while avoiding the need for separate capacitor and transistor components, thus not significantly increasing overall device complexity.
Solution Approach 2:
The patent merges the storage function (charge trapping) with the gate structure of the trench transistor. The charge-trapping layer is integrated into the gate stack rather than being a separate component, combining the transistor control function with non-volatile storage in a single unified structure, thereby minimizing complexity increase.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The non-volatile memory maintains fast access times while eliminating the need for data refreshing, reducing power consumption and enhancing memory capacity without increasing device size.
Implementation Method 1
a tunneling dielectric layer is disposed between the charge-trapping layer and the substrate
Implementation Method 2
the charge-trapping layer disposed between the substrate and the second gate
Implementation Method 3
A top dielectric layer is disposed between the charge-trapping layer and the second gate
Data Source
AI summary
A nonvolatile memory is provided. The memory includes a select transistor and a trench transistor. The select transistor is formed on the substrate. The select transistor includes a first gate formed on the substrate and first and second source/drain regions formed in the substrate next to the first gate. The trench transistor is formed in the substrate. The trench transistor includes a second gate formed in the trench of substrate, an electron trapping layer formed between the second gate and the trench and second and third source/drain regions formed in the substrate next to the second gate. The select transistor and the trench transistor share the second source/drain region.