Nonvolatile Memory Tri-State Latch Dump Sequence Optimization

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Conventional nonvolatile memory devices face inefficiencies in programming operations due to sequential dump sequence operations, which lead to increased overhead and potential data damage during simultaneous latch data reflection, especially when dealing with multiple latches.

Innovation Solution

The implementation of a nonvolatile memory device with tri-state latches and a page buffer circuit that allows simultaneous reflection of data from multiple latches to a sensing node, using a calibration transistor to discharge the sensing node and restore damaged data through tri-state latch operations, thereby reducing dump time and preventing data damage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If sequential dump sequence operations are used in conventional nonvolatile memory devices, then data from multiple latches can be reflected to the sensing node, but programming overhead increases and data damage may occur

Engineering Contradiction:

Improvedata integrityVSAvoidprogramming overhead

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent precharges the transfer node before simultaneously reflecting data from multiple latches to the sensing node. This preliminary action ensures that the transfer node is ready to receive and transfer data without causing data damage, while enabling parallel operation that reduces programming overhead and time

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces a transfer node as an intermediary between the latches and the sensing node. This transfer node facilitates the simultaneous reflection of data from multiple latches by providing a intermediate storage point that can be precharged and then transferred to the sensing node, preventing data damage while enabling parallel operations

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If simultaneous reflection of multiple latch data to sensing node is implemented, then dump time is reduced, but data damage may occur during the operation

Engineering Contradiction:

Improvedump speedVSAvoiddata integrity

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The transfer node is precharged before simultaneously reflecting data from multiple latches to the sensing node. This preliminary charging ensures that the transfer node has the necessary voltage level to safely transfer data without causing data damage, enabling fast parallel operations while maintaining data integrity

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent uses the precharged transfer node as a cushioning mechanism that protects against data damage during simultaneous latch data reflection. The precharged state acts as a protective buffer that prevents harmful voltage conflicts or data corruption that could occur during parallel data transfer operations

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS20240363172A1Nonvolatile memory devices, storage devices including the same, and methods of operating the same

Publication Date: 2024.10.31 SAMSUNG ELECTRONICS CO LTD

AI summary

A nonvolatile memory device includes a plurality of tri-state latches, a sensing node circuit configured to electrically couple a sensing node therein to a bitline of the memory device, a transfer node circuit configured to electrically couple a transfer node therein to the plurality of tri-state latches, and a node connection circuit configured to electrically connect the transfer node to the sensing node. In addition, the transfer node circuit and the node connection circuit are collectively configured to simultaneously reflect data stored in at least two of the plurality of tri-state latches to the sensing node, in response to a dump sequence operation.