Nonvolatile Memory Device Verify Voltage Control
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Solution Overview
Problem
The high degree of integration in semiconductor memory devices, particularly in nonvolatile memory devices, leads to manufacturing defects such as progressive resistance in word lines, causing variations in resistance and making it difficult to read data accurately due to the stacked structure, which existing technologies struggle to detect and address effectively.
Innovation Solution
A nonvolatile memory device with a peripheral circuit that performs a program operation involving multiple verify voltages and additional verify voltages to detect and process abnormal distributions in threshold voltages of memory cells, ensuring successful programming and preventing data loss by identifying and reporting progressive resistance defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cells are stacked on top of one another to improve integration, then the degree of integration increases, but the height of vias connected with word line lines increases causing manufacturing defects and resistance variation
Solution Approach 1:
The patent segments the verification process into multiple stages (first verify with initial verify voltage, second verify with increased verify voltage, third verify with further increased verify voltage). This segmentation allows detection of progressive resistance defects at different severity levels, enabling early intervention before complete failure occurs, thus resolving the contradiction between high integration and manufacturing reliability
2Productivity
If memory cells are stacked on top of one another to improve integration, then the degree of integration increases, but the resistance of word lines varies making it difficult to read data accurately
Solution Approach 1:
The patent dynamically adjusts the verify voltage across three different stages (initial verify voltage, increased verify voltage, and further increased verify voltage) based on the detected threshold voltage distribution. This dynamic adjustment compensates for resistance variations in stacked memory structures, maintaining data reading accuracy despite high integration levels
Solution Approach 2:
The patent implements a feedback mechanism where the result of each verify stage is used to determine the next action. If the first verify fails, the system increases the verify voltage for the second verify. If the second verify fails, it increases further for the third verify. This feedback loop continuously adapts to detected abnormalities, ensuring accurate data reading in highly integrated stacked memory structures
3Reliability
If additional verify voltages are applied to detect abnormal distributions, then the detection capability improves, but the program operation complexity increases
Solution Approach 1:
The patent performs preliminary verification actions in a structured sequence before finalizing the program operation. The first verify with initial voltage checks for basic abnormalities, the second verify with increased voltage detects more severe issues, and the third verify with further increased voltage confirms critical defects. This preliminary action approach systematically improves detection capability while managing complexity through a predetermined verification sequence
Data Source
AI summary
A nonvolatile memory device includes a memory cell array including a plurality of memory cells, and a peripheral circuit that performs a program operation of repeatedly performing a program loop. The program loop includes performing a program by applying a program voltage to memory cells selected from the plurality of memory cells, and a first verify by applying a plurality of verify voltages to the selected memory cells. The peripheral circuit completes the program operation in response to a success of the first verify, performs a second verify by applying an additional verify voltage different from the plurality of verify voltages to the selected memory cells, and determines the program operation has failed in response to a failure of the second verify.