Virtual Partitioning for Non-Volatile Memory Testing

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Solution Overview

Problem

Existing non-volatile memory testing methods in electronic devices are limited in their ability to generate detailed results without requiring additional memory for storing test applications and data, and they often cannot accurately identify defective memory cells during the manufacturing process.

Innovation Solution

The implementation of a system-on-a-chip (SoC) with a testing mode that allows for the creation of virtual partitions in non-volatile memory, enabling a test application to directly access physical addresses and generate detailed test results without additional memory, by using a separate access layer in addition to the flash translation layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a dedicated test memory is used to store test applications and data, then testing capability is improved, but device complexity and memory requirements increase

Engineering Contradiction:
Improvetesting capabilityVSAvoidmemory requirements
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the test application and test data storage with the main non-volatile memory by creating a virtual partition, eliminating the need for a separate dedicated test memory component. The test application is stored in a first region of the non-volatile memory, and test data is stored in a second region, both within the same memory device.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The non-volatile memory is segmented into different regions with specific functions: a first region for storing the test application, a second region for storing test data, and a third region for storing production applications. This segmentation allows the memory to serve multiple purposes without requiring additional dedicated memory components.

Inventive Principle:
Principle #1Segmentation

2Ease of operation

If the translation layer maps all physical addresses, then normal operation is improved, but testing precision deteriorates because actual memory locations cannot be determined

Engineering Contradiction:
Improvenormal operationVSAvoiddefective cell identification accuracy
Core Design Contradiction:
Ease of operationVSMeasurement precision

Solution Approach 1:

The translation layer is segmented to handle different address spaces: it maps logical addresses to physical addresses in the first and second regions (test regions), but provides direct physical address access to the third region (production region). This allows test applications to precisely identify defective cells in production regions while maintaining normal operation in test regions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The translation layer acts as an intermediary that behaves differently depending on the region being accessed. For test regions, it performs full address mapping; for the production region, it allows direct physical address access, enabling test applications to determine actual memory locations of defective cells.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Measurement precision

If virtual partitions are created for testing, then testing detail is improved, but device complexity increases due to additional access layers

Engineering Contradiction:
Improvetest result detailVSAvoidsoftware structure
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The test application serves multiple functions: it can execute tests in the first region, store results in the second region, and access production memory locations directly through the third region. This multi-functionality reduces the need for separate dedicated testing components and simplifies the overall system architecture.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The non-volatile memory device performs its own self-testing through the test application stored within it. The device uses its own memory structure to conduct tests, store results, and identify defective cells, eliminating the need for external testing equipment and reducing system complexity.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS8683456B2Test partitioning for a non-volatile memory
Publication Date: 2014.03.25 APPLE INC
  • US8683456B2 patent drawing
  • US8683456B2 patent drawing
  • US8683456B2 patent drawing

AI summary

Systems and methods are provided for testing a non-volatile memory, such as a flash memory. The non-volatile memory may be virtually partitioned into a test region and a general purpose region. A test application may be stored in the general purpose region, and the test application can be executed to run a test of the memory locations in the test region. The results of the test may be stored in the general purpose region. At the completion of the test, the test results may be provided from the general purpose region and displayed to a user. The virtual partitions may be removed prior to shipping the electronic device for distribution.