Nonvolatile Memory Device With Volatile Cache And Dual Controller Architecture

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Solution Overview

Problem

Current semiconductor memory devices face challenges in maintaining data integrity and capacity within a restricted area due to the volatility of DRAM, which loses data at power-off and has large unit cell sizes, making it difficult to increase capacity.

Innovation Solution

A nonvolatile memory device with a volatile memory cache and controllers that manage data transmission and storage through separate buses, allowing for efficient data handling and storage by determining cache hits and misses based on tags, enabling selective storage and retrieval of data.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If DRAM is used for main memory to achieve fast response speed, then operation speed is improved, but data is lost when power is shut off

Engineering Contradiction:
Improveoperation speedVSAvoiddata retention
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The memory system is divided into two distinct memory types: volatile memory (DRAM) for fast operations and nonvolatile memory for data retention. The controller segments memory management by determining which data to store in which memory type based on access patterns and data characteristics, thereby achieving both fast access and data retention.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The controller acts as an intermediary between the volatile and nonvolatile memory components, managing data transfer and coherence between them. It monitors cache status and automatically transfers data between memory types, allowing the system to maintain fast access speeds while ensuring data persistence.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Quantity of substance

If DRAM unit cell size is reduced to increase capacity, then storage capacity increases, but manufacturing precision requirements increase

Engineering Contradiction:
Improvestorage capacityVSAvoidunit cell fabrication precision
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

Instead of solely reducing unit cell dimensions to increase capacity, the system adds a temporal and functional dimension by implementing a hybrid memory architecture with cache layers and intelligent data placement. This allows capacity expansion through efficient data management across multiple memory types rather than purely through miniaturization.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Productivity

If volatile memory cache is added to manage data between memory types, then data access efficiency is improved, but device complexity increases

Engineering Contradiction:
Improvedata access efficiencyVSAvoidcontroller architecture complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The controller implements self-service mechanisms by automatically monitoring cache hit rates, identifying frequently accessed data, and making autonomous decisions about data placement between volatile and nonvolatile memory. This self-managing approach reduces the need for complex external control logic while maintaining high data access efficiency.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system dynamically adjusts operational parameters such as cache size allocation, data placement policies, and memory access patterns based on observed workload characteristics. By changing these parameters adaptively rather than using fixed complex control logic, the system achieves high productivity with manageable complexity.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11614866B2Nonvolatile memory device and operation method thereof
Publication Date: 2023.03.28 SAMSUNG ELECTRONICS CO LTD
  • US11614866B2 patent drawing
  • US11614866B2 patent drawing
  • US11614866B2 patent drawing

AI summary

A nonvolatile memory device includes a nonvolatile memory, a volatile memory being a cache memory of the nonvolatile memory, and a first controller configured to control the nonvolatile memory. The nonvolatile memory device further includes a second controller configured to receive a device write command and an address, and transmit, to the volatile memory through a first bus, a first read command and the address and a first write command and the address sequentially, and transmit a second write command and the address to the first controller through a second bus, in response to the reception of the device write command and the address.