Nonvolatile Memory Even-Odd Sensing for Program Voltage Compensation
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Solution Overview
Problem
The existing program operations in nonvolatile memory devices, such as flash memory, require multiple repetitions of incremental step programming pulses, leading to increased time due to repeated verify operations, especially when distribution sagging of threshold voltages occurs, which is not effectively addressed by current two-step verify schemes.
Innovation Solution
A memory device and method that includes a first program loop with even and odd sensing on bit lines, followed by a second program loop with compensation voltage levels based on the results of the first verify operation, allowing for optimized program voltage adjustments to address distribution sagging and reduce the number of program loops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If incremental step programming pulses with multiple program loops are used, then data can be written into nonvolatile memory cells, but the time required for program operation increases due to repeated verify operations
Solution Approach 1:
The patent segments the bit lines into even-numbered and odd-numbered groups, performing verify operations on even bit lines first, then odd bit lines. This segmentation allows the verify operation to be divided into two separate sensing phases, enabling more efficient voltage compensation strategies that reduce the total number of program loops needed, thereby reducing overall program operation time while maintaining data writing capability
Solution Approach 2:
The patent dynamically changes the program voltage level based on verify operation results. After verifying even bit lines, the control logic determines whether to maintain, increase, or decrease the program voltage level for subsequent odd bit line programming. This parameter adjustment optimizes the programming process by adapting voltage levels to actual memory cell states, reducing unnecessary program loops and verify operations
2Measurement precision
If the number of verify operations is increased to ensure accurate data writing, then programming accuracy improves, but the time required to write data significantly increases
Solution Approach 1:
The patent implements periodic verify operations structured in two phases: first verifying even bit lines, then verifying odd bit lines. This periodic structure allows the system to perform necessary verification checks while maintaining a rhythmic, efficient operation pattern that minimizes idle time and reduces overall programming time while ensuring accurate data writing through systematic verification
3Reliability
If distribution sagging of threshold voltages occurs, then memory cell performance degrades, but existing two-step verify schemes do not effectively address this issue
Solution Approach 1:
The patent implements feedback control where the control logic analyzes verify operation results from even bit lines and uses this information to determine the appropriate program voltage level for odd bit line programming. This feedback mechanism detects threshold voltage distribution sagging and compensates by adjusting voltage levels, effectively addressing performance degradation without requiring complex external intervention
Solution Approach 2:
The patent makes the verify scheme dynamic by allowing the program voltage level to change based on verify results. The control logic dynamically adjusts whether to increase, maintain, or decrease voltage levels for subsequent programming cycles, creating an adaptive system that responds to distribution sagging conditions without requiring a completely complex verify scheme structure
Data Source
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AI summary
A memory device for improving the speed of a program operation and an operating method thereof is provided. The memory device includes a memory cell array including a plurality of memory cells, a voltage generator configured to generate voltages for one or more program operations and a verify operation performed on the plurality of memory cells, a control logic configured to perform a control operation on the plurality of memory cells so that a first program and a second program loop are performed, a second program operation being performed based on a compensation voltage level determined based on a result of the first verify operation, and a plurality of bit lines connected to the memory cell array, wherein the first verify operation includes first even sensing and second even sensing on even-numbered bit lines, and first odd sensing and second odd sensing on odd-numbered bit lines.