Nonvolatile Memory Data Invalidation via Voltage Detection
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in power management, particularly in nonvolatile memory systems where data retention and security are critical, leading to increased design complexity and power consumption, as well as potential data leakage when power is interrupted.
Innovation Solution
A nonvolatile memory system incorporating a memory cell array with a voltage detector and control logic that invalidates data by overwriting memory cells with '0' or '1' based on power supply voltage variations, using a super capacitor for power-off operations, and selectively invalidating data in designated areas to prevent security data leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If data is retained in nonvolatile memory during power interruption, then data retention is improved, but data security deteriorates due to potential data leakage
Solution Approach 1:
The voltage detector monitors power supply voltage in advance and generates a voltage variation signal before complete power loss occurs. The control logic receives this signal and proactively invalidates data by overwriting memory cells with predetermined values (0 or 1) before the power interruption completes, preventing data leakage while maintaining security.
Solution Approach 2:
Instead of attempting to protect data during power interruption, the patent inverts the approach by deliberately destroying data through overwrite operations. The control logic inverts the normal data storage function by writing predetermined values to memory cells, transforming the memory from a data retention device to a data destruction device when voltage variation is detected.
2Reliability
If data invalidation is performed on all memory cells, then data security is improved, but power consumption increases
Solution Approach 1:
The patent applies local quality by selectively invalidating data only in specific memory regions rather than uniformly across all memory cells. The memory cell array is divided into multiple regions, and the control logic determines which regions require invalidation based on the voltage variation signal and system state, applying the overwrite operation only where necessary to maintain security while reducing overall power consumption.
Solution Approach 2:
The patent uses partial action by performing data invalidation on only a portion of the memory cell array rather than all cells. When voltage variation is detected, the control logic selectively applies overwrite operations to specific regions or banks of memory cells that contain sensitive data, achieving adequate security through partial invalidation rather than exhaustive coverage of all memory cells.
3Use of energy by moving object
If selective data invalidation is implemented, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent segments the memory cell array into multiple distinct regions, each potentially containing different types of data with different security requirements. The control logic is designed to work with this segmented structure, allowing independent invalidation of specific regions based on voltage variation signals and data classification, thereby reducing power consumption by avoiding unnecessary invalidation of entire memory arrays.
Solution Approach 2:
The control logic acts as an intermediary between the voltage detector and the memory cell array. It receives the voltage variation signal from the detector and mediates the invalidation process by determining which specific memory regions require data destruction. This intermediary function simplifies the overall system by centralizing the decision-making logic in a dedicated component rather than distributing complexity throughout the memory structure.
4Reliability
If voltage detection and automatic invalidation are added, then data security is improved, but device complexity increases
Solution Approach 1:
The voltage detector enables the memory system to self-monitor its own power supply status and automatically trigger data invalidation when voltage variation is detected. The system serves itself by detecting power interruptions and initiating protective invalidation operations without requiring external intervention or complex external control circuits, thereby improving security while adding only minimal internal circuitry.
Solution Approach 2:
The voltage detector and control logic are integrated directly into the memory device structure, merging the power monitoring and data protection functions with the existing memory architecture. This consolidation combines multiple functions (voltage detection, signal generation, invalidation control) into unified circuit blocks that work seamlessly with the memory cell array, improving security without proportionally increasing overall device complexity.
Data Source
AI summary
A nonvolatile memory is provided which includes a memory cell array including a plurality of nonvolatile memory cells; a decoder connected with the memory cell array through a plurality of word lines; a data input/output circuit connected with the memory cell array through a plurality of bit lines; a voltage detector configured to detect a variation in a power supply voltage to output a voltage variation signal; and control logic configured to control the decoder and the data input/output circuit such that data stored at the memory cell array is invalidated in response to the voltage variation signal.