Nonvolatile Memory Wiring with Copper-Tungsten Composite
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Solution Overview
Problem
The miniaturization of wirings in nonvolatile semiconductor memory devices leads to increased wiring resistance, posing a challenge in maintaining effective circuit design and performance.
Innovation Solution
The implementation of a wiring layer structure in the peripheral region with a first portion made of copper and a second portion made of tungsten, where the copper portion is embedded in the interlayer insulating film and the tungsten portion is above it, reducing resistance by optimizing the material distribution and embedding technique.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If wiring miniaturization is advanced to support high-density memory structures, then device integration density is improved, but wiring resistance increases
Solution Approach 1:
The patent applies local quality by using different materials for different portions of the wiring structure. Specifically, copper is used for bit line wiring and tungsten is used for source/drain wiring, with each material selected based on its electrical properties being optimal for its specific function. The copper interlayer insulating film is also localized to specific regions where low resistance is critical, thereby reducing overall wiring resistance while maintaining high integration density.
Solution Approach 2:
The patent employs composite materials by combining copper and tungsten in the wiring structure. The copper interlayer insulating film is formed in specific regions and combined with conventional insulating materials, creating a composite structure that leverages the low resistance of copper in critical paths while maintaining the structural integrity and insulation properties of traditional materials in other areas.
2Reliability
If copper interlayer insulating film is formed in specific regions to reduce resistance, then wiring resistance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the interlayer insulating film formation into distinct regions. The copper interlayer insulating film is formed only in specific regions where low resistance is required, rather than uniformly across the entire device. This segmented approach allows selective reduction of resistance in critical areas while avoiding the need to modify the entire manufacturing process, thereby limiting the increase in manufacturing complexity.
Solution Approach 2:
The patent uses a copper interlayer insulating film as an intermediary element between conventional wiring structures and low-resistance requirements. This copper film acts as a mediator that provides the necessary electrical properties in specific regions without requiring complete redesign of the wiring architecture, thus reducing resistance while maintaining compatibility with existing manufacturing processes.
Data Source
AI summary
According to one embodiment, a nonvolatile semiconductor memory device includes: an interlayer insulating film; an element separating region separating a semiconductor layer in the memory cell region; a gate electrode provided on one of plurality of semiconductor regions in the memory cell region; a contact electrode having a sidewall in contact with the interlayer insulating film and electrically connected to the one of the plurality of semiconductor regions in the memory cell region; a first wiring layer connected to an upper end of the contact electrode in the memory cell region; and a second wiring layer in a third direction, having an upper end higher than the upper end of the contact electrode, having a lower end lower than the upper end of the contact electrode, and having a sidewall at least partly in contact with the interlayer insulating film in the peripheral region.