Nonvolatile Memory Write Management via Request Grouping

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Solution Overview

Problem

In memory systems that use nonvolatile memory, such as SSDs with NAND flash memory, the frequent issuance of write requests for the same logical address or the combination of write and trim requests at short intervals leads to premature wear of the nonvolatile memory, as data written in response to earlier requests becomes invalid soon after.

Innovation Solution

The implementation of a technique that manages write operations and trim requests by using a locked data list and a write management table to track the status of write commands and trim commands, allowing for delayed write completion and efficient use of storage areas in the nonvolatile memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If write requests are immediately executed for each individual request, then response time to host is improved, but nonvolatile memory wears prematurely due to frequent write operations

Engineering Contradiction:
Improveresponse timeVSAvoidmemory wear
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The system performs preliminary grouping of write requests before execution. The memory controller accumulates multiple write requests targeting the same logical address into a single write unit, then executes them together. This preliminary action reduces the total number of write operations to the nonvolatile memory while still satisfying all individual write requests, thereby reducing memory wear without significantly increasing response time.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If delayed write completion is used to improve storage efficiency, then storage area utilization is improved, but write operation latency increases

Engineering Contradiction:
Improvestorage efficiencyVSAvoidwrite latency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The system performs preliminary grouping of write requests by logical address before executing delayed write completion. By organizing write requests into groups targeting the same logical address in advance, the system can efficiently consolidate multiple writes into single physical write operations. This preliminary organization enables the delayed write completion mechanism to achieve better storage efficiency while minimizing the additional latency introduced by waiting for request accumulation.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If multiple write requests to the same logical address are consolidated, then memory wear is reduced, but write operation complexity increases

Engineering Contradiction:
Improvememory wearVSAvoidwrite management complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system introduces a write management table as an intermediary data structure between the host interface and the nonvolatile memory. This table tracks write requests by logical address, consolidates multiple requests targeting the same address, and manages the grouping process. By using this intermediary, the system reduces memory wear through consolidated writes while offloading the complexity of request management to a dedicated data structure, simplifying the overall control logic.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20250123756A1Information processing apparatus
Publication Date: 2025.04.17 KIOXIA CORP
  • US20250123756A1 patent drawing
  • US20250123756A1 patent drawing
  • US20250123756A1 patent drawing

AI summary

According to one embodiment, an information processing apparatus includes a nonvolatile memory and a CPU. The CPU stores, to the nonvolatile memory, first data, and management data including information equivalent to a write command associated with the first data and designating a first LBA range, and performs a first transmission of the write command to a memory system. When writing of second data to a second LBA range including a third LBA range that is at least a portion of the first LBA range or deallocation of the second LBA range is requested before a second response to the write command is received, the CPU transmits, to the system, a command to cancel writing to at least the third LBA range from writing of the first data to the first LBA range in accordance with the write command.