Non-volatile Memory Write Protection Data Structure Latency Reduction
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Solution Overview
Problem
The increasing memory capacity in non-volatile data storage devices leads to increased size of write protection maps, resulting in significant write latency as the device searches for write-protected data, especially when the write address is near the beginning or end of the address space.
Innovation Solution
A write protection data structure is implemented, which includes entries corresponding to ranges of memory addresses with indications of write protection, allowing for faster access and reducing latency by eliminating the need for a full search of the write protection map in many cases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the memory capacity is increased, then the storage capacity is improved, but the write protection map size increases causing increased write latency
Solution Approach 1:
The write protection map is segmented into multiple levels: a write protection data structure with entries covering large address ranges, and a detailed write protection map for finer-grained addressing. This hierarchical segmentation allows the system to quickly determine write protection status for large portions of memory without searching the entire map, thereby reducing write latency while supporting large memory capacities.
Solution Approach 2:
The invention introduces an additional dimension of address range management by creating entries in the write protection data structure that map to large address ranges (e.g., 512 MB or larger). This dimensional approach allows the system to skip through large portions of the write protection map that are not relevant to the current write operation, significantly reducing the search time while maintaining accurate write protection control.
2Adaptability or versatility
If the write protection map size is increased, then the coverage of memory addresses is improved, but the search time through the map increases
Solution Approach 1:
The address space coverage is achieved through segmentation of the write protection information into hierarchical levels. The write protection data structure provides coarse-grained coverage with large address ranges, while the detailed write protection map provides fine-grained coverage. This segmentation allows the system to maintain comprehensive address space coverage without having to search the entire detailed map for every write operation.
Solution Approach 2:
The write protection data structure acts as an intermediary between the write operation and the detailed write protection map. It provides a quick lookup mechanism that determines whether a write operation needs to search the detailed map at all, or can proceed directly based on the coarse-grained information, thereby reducing search time while maintaining comprehensive coverage.
3Measurement precision
If a full search of the write protection map is performed, then the accuracy of write protection determination is improved, but the write latency increases
Solution Approach 1:
The write protection determination process is segmented into two stages: first, a quick lookup in the write protection data structure using the write address to determine the relevant address range; second, only if necessary, a search in the detailed write protection map. This segmentation maintains measurement precision for write protection determination while significantly reducing write latency by avoiding unnecessary full map searches.
Solution Approach 2:
The system performs partial action by using the write protection data structure to determine the relevant address range before performing the full search in the detailed write protection map. This partial lookup provides sufficient information for most write operations, avoiding the excessive action of searching the entire map when not necessary, thus reducing latency while maintaining adequate accuracy.
Data Source
AI summary
A data storage device includes a write protection data structure that includes a first set of entries corresponding to a first set of ranges of memory addresses. A first indication stored in an entry, in the first set of entries, corresponds to an absence of write-protected data between a lowest address of the range of addresses corresponding to the entry and a highest address of a memory. A second indication stored in the entry corresponds to write-protected data within the range of addresses. The data storage device also includes a write protection map that includes a second set of entries corresponding to a second set of ranges of the memory addresses. The device is configured to locate, in the write protection data structure, an entry corresponding to a range of memory addresses.