Nonvolatile Memory Page-Buffer Capacitors for 3D Circuit Scaling
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in reducing the area occupied by read and write circuits, particularly as they approach physical scaling limits in two-dimensional structures, necessitating the development of three-dimensional configurations.
Innovation Solution
The implementation of a nonvolatile semiconductor memory device with a reduced area for read and write circuits is achieved by incorporating a memory cell array, a read and write circuit, and control logic, which includes a capacitor for bit data storage and utilizes a DRAM structure for the temporary storage circuit to minimize transistor and capacitor requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional read and write circuits are implemented in two-dimensional structure, then circuit functionality is maintained, but area occupied by the circuit increases
Solution Approach 1:
The patent transitions from a two-dimensional circuit layout to a three-dimensional structure by stacking memory cell arrays vertically. Multiple memory cell arrays are arranged in layers along the vertical direction, allowing the read and write circuits to serve multiple layers simultaneously. This dimensional change reduces the horizontal area occupied by the circuit while maintaining full functionality across all memory layers.
Solution Approach 2:
The read and write circuits are designed to handle multiple memory cell arrays vertically stacked. A single set of read and write circuits can access and operate on memory cells from different layers through vertical bit lines, making the circuit multi-functional. This universal design allows one circuit instance to serve multiple memory layers, reducing the total circuit area required.
2Quantity of substance
If more transistors and capacitors are used in read and write circuits, then data storage capability is improved, but area occupied by the circuit increases
Solution Approach 1:
By stacking memory cell arrays vertically, the patent enables data storage capacity to increase through the vertical dimension rather than expanding horizontally. Multiple layers of memory cells can be accessed by the same read and write circuit, increasing the quantity of stored data without proportionally increasing the circuit area.
Solution Approach 2:
The memory system is segmented into multiple vertically stacked memory cell arrays, each accessible through shared bit lines. This segmentation allows the total data storage capacity to be distributed across layers, with the read and write circuits efficiently managing access to segmented memory portions without requiring dedicated circuits for each segment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the physical area occupied by the read and write circuits, enhancing operational efficiency and reliability while maintaining data retention even in power interruptions.
Implementation Method 1
The read and write circuit may include at least one capacitor configured to store bit data
Data Source
AI summary
Provided herein may be a nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device may include a memory cell array, a read and write circuit, and a control logic. The memory cell array may include a plurality of nonvolatile memory cells. The read and write circuit may be configured to perform a program operation or a read operation on nonvolatile memory cells that are selected from among the plurality of nonvolatile memory cells. The control logic may be configured to control an operation of the read and write circuit. The read and write circuit may include at least one capacitor configured to store bit data.