Non-Volatile Register Control for Faster Low-Power Data Retention

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Solution Overview

Problem

Existing semiconductor devices face challenges in reducing time and power dissipation during data saving and restoration, and they experience unnecessary writing and loading in non-volatile memories, leading to increased power dissipation and vulnerability to power failures.

Innovation Solution

A semiconductor device with non-volatile registers that include flip-flops for holding data in both volatile and non-volatile manners, utilizing a control method with write and load instructions to manage data transfer between these registers, reducing the frequency of non-volatile memory rewriting and loading, and enhancing resistance to power failures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If data is saved to external storage before power supply stop, then data retention is ensured, but time delay and power dissipation due to data transfer increase

Engineering Contradiction:
Improvedata retentionVSAvoiddata transfer time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent merges the volatile memory (flip-flop) and non-volatile memory (non-volatile element) into a single integrated storage unit. The flip-flop holds data in a volatile manner during operation, while the non-volatile element simultaneously maintains the same data in a non-volatile manner, eliminating the need for separate data transfer to external storage and reducing time delay.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The non-volatile element acts as an intermediary between the volatile flip-flop and external storage. Instead of transferring data from the flip-flop to external storage, the non-volatile element directly maintains a copy of the data, serving as a buffer that eliminates the need for lengthy external data transfer operations.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If data is saved to external storage before power supply stop, then data retention is ensured, but power dissipation due to data transfer increases

Engineering Contradiction:
Improvedata retentionVSAvoiddata transfer power
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent merges the volatile memory (flip-flop) and non-volatile memory (non-volatile element) into a single integrated storage unit. The flip-flop holds data in a volatile manner during operation, while the non-volatile element simultaneously maintains the same data in a non-volatile manner, eliminating the need for separate data transfer to external storage and reducing power dissipation.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The non-volatile element acts as an intermediary between the volatile flip-flop and external storage. Instead of transferring data from the flip-flop to external storage, the non-volatile element directly maintains a copy of the data, serving as a buffer that eliminates the need for power-consuming external data transfer operations.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If all volatile latches save data to non-volatile memory upon power-off, then data retention is ensured, but unnecessary writing occurs increasing power dissipation

Engineering Contradiction:
Improvedata retentionVSAvoidwriting power
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

Instead of saving data from all volatile latches to non-volatile memory upon every power-off, the patent applies partial action by only saving data when the power supply voltage actually drops below a threshold level. This selective approach avoids unnecessary writing operations and reduces power dissipation while still ensuring data retention when needed.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent monitors the power supply voltage parameter and triggers data saving only when this parameter changes to indicate an actual power-off condition. By using voltage threshold detection, the system changes its behavior based on the actual power state, avoiding unnecessary writing operations that would occur with frequent or unconditional saving.

Inventive Principle:
Principle #35Parameter changes

4Reliability

If non-volatile memory is rewritten for each power-off, then data retention is ensured, but power dissipation for rewriting increases

Engineering Contradiction:
Improvedata retentionVSAvoidrewriting power
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

Instead of rewriting all non-volatile memory upon every power-off, the patent applies partial action by only rewriting data when the power supply voltage actually drops below a threshold level. This selective rewriting approach avoids unnecessary power consumption while ensuring data retention when actual power-off occurs.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent monitors the power supply voltage parameter and triggers data rewriting only when this parameter changes to indicate an actual power-off condition. By using voltage threshold detection, the system changes its behavior based on the actual power state, avoiding unnecessary rewriting operations that would consume power.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9135988B2Semiconductor device and control method of the same
Publication Date: 2015.09.15 NEC CORP
  • US9135988B2 patent drawing
  • US9135988B2 patent drawing
  • US9135988B2 patent drawing

AI summary

A semiconductor device includes non-volatile registers, each including a holding circuit to hold data in a volatile manner and a non-volatile element. An address is allocated to each of the non-volatile registers. A non-volatile register control circuit performs control such that, in response to a write instruction, data held in the holding circuit is written to the non-volatile element in the non-volatile register having the address specified by the instruction and in response to a load instruction, data held in the non-volatile element is held in the holding circuit in the non-volatile register having the address specified by the instruction.