Non-Volatile Cell Based Register for Memory Configuration Data
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Solution Overview
Problem
Traditional memory device structures are unsuitable for non-volatile storage of configuration data, lacking robustness and requiring external controllers for error correction, and face challenges in writing data at power-down or reading data at power-up due to voltage and timing dependencies.
Innovation Solution
A robust self-contained latch unit using non-volatile memory cells with addressable arrays, including sense amplifiers and capacitors, for reliable storage and retrieval of configuration data, enabling independent operation within memory chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional memory device structures are used for configuration data storage, then volatile memory can be implemented, but the system lacks robustness and requires external controllers for error correction
Solution Approach 1:
The memory device is configured to autonomously perform error detection and correction operations on configuration data without requiring external controllers. The device includes error correction circuitry integrated within the memory device itself, enabling it to self-correct errors in configuration data stored in non-volatile memory cells, thereby eliminating dependency on external error correction mechanisms.
Solution Approach 2:
The memory device is divided into functional segments including configuration data storage area, error detection circuitry, and error correction circuitry. This segmentation allows the error correction functionality to be distributed within the device structure, with specific circuit blocks dedicated to detecting and correcting errors in configuration data, improving overall reliability without requiring a single complex external controller.
2Ease of operation
If traditional memory structures are used, then external controllers can manage data operations, but writing data at power-down or reading data at power-up becomes challenging due to voltage and timing dependencies
Solution Approach 1:
Configuration data is written to non-volatile memory cells before power-down occurs, ensuring data is stored in a state that can be reliably retrieved after power restoration. The device is configured to complete write operations to non-volatile storage prior to power loss, and to automatically retrieve this data upon power-up without requiring complex voltage sequencing or timing coordination.
Solution Approach 2:
The memory device utilizes non-volatile memory cells that maintain data across power cycles, changing the operational parameters from volatile to non-volatile storage. This allows configuration data to be read at power-up without the voltage and timing constraints that plague traditional volatile memory systems, as the non-volatile cells retain data independently of power state transitions.
3Duration of action of stationary object
If non-volatile memory cells are used for configuration data storage, then data can be retained without power, but the memory device structure becomes unsuitable for traditional storage operations
Solution Approach 1:
The memory device is configured to perform multiple functions using the same non-volatile memory cells: serving both as configuration data storage (retaining data without power) and as operational memory for traditional storage operations. The device includes control circuitry that manages both configuration data access and regular memory operations, enabling the non-volatile cells to adapt to different operational modes without requiring separate storage structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Ensures reliable non-volatile storage and retrieval of configuration data, independent of external controllers, with improved robustness and reduced dependency on power states for writing and reading operations.
Implementation Method 1
a first non-volatile capacitor of the latch unit and a second line, where the first capacitor is configured to store a charge representing one or more bits
Data Source
AI summary
Methods, systems, and devices for system and method for reading and writing memory management data through a non-volatile cell based register are described. A memory device may include a set of latch units addressable via a set of row lines and a set of column lines. Each latch unit may include a sense amplifier coupled with a first line and a first non-volatile capacitor coupled with the first line and a second line, where the first capacitor is configured to store a charge representing one or more bits. Additionally, each latch unit may include a second capacitor coupled with the first line and a third line, where the second capacitor is configured to amplify a voltage at the first line based on the charge stored in the first capacitor.