Nonvolatile Semiconductor Storage Via Hole Formation
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Solution Overview
Problem
Existing semiconductor storage devices face challenges in miniaturizing design rules for trace patterns and increasing integration density, leading to increased costs due to the need for multiple photo engraving processes and complex three-dimensional memory cell stacking.
Innovation Solution
A nonvolatile semiconductor storage apparatus with a substrate, insulating layers, columnar semiconductors, and conductor layers with bent end portions and contact plugs, allowing for a single process to form via holes and reduce the number of manufacturing steps, thereby simplifying the formation of word-line electrodes and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple photo engraving processes are used to form via holes for each word-line electrode layer, then manufacturing precision is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent combines the formation of via holes for multiple word-line electrode layers (first, second, and third conductor layers) into a single photo engraving process. By forming all via holes simultaneously before stacking the conductor layers, the method eliminates the need for separate photo engraving processes for each layer, thereby reducing manufacturing process complexity while maintaining precision through unified patterning
Solution Approach 2:
The patent performs the photo engraving process to form via holes in the insulating layer before depositing the conductor layers. This preliminary action allows all via hole patterns to be established in advance, enabling subsequent conductor layer deposition to proceed without requiring additional photo engraving steps for each layer
2Productivity
If three-dimensional memory cell stacking is implemented to increase integration density, then productivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell arrangement to three-dimensional stacking by vertically arranging multiple conductor layers (first, second, and third word-line electrode layers) above the substrate. This dimensional change increases integration density by utilizing the vertical space, allowing multiple memory cell layers to be stacked without requiring further miniaturization of the lateral design rules
Data Source
AI summary
According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage apparatus including: a substrate; a columnar semiconductor disposed perpendicular to the substrate; a charge storage laminated film disposed around the columnar semiconductor; a first conductor layer that is in contact with the charge storage laminated film and that has a first end portion having a first end face; a second conductor layer that is in contact with the charge storage laminated film, that is separated from the first conductor layer and that has a second end portion having a second end face; a first contact plug disposed on the first end face; and a second contact plug disposed on the second end face.