Nonvolatile Single-Poly Memory Device with Dual-Unit Cell Design
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Solution Overview
Problem
Existing non-volatile single-poly memory devices face challenges in achieving high data correctness and flexibility in semiconductor processes, particularly when operating at low voltages and requiring compatibility with logic processes.
Innovation Solution
A non-volatile single-poly memory device design featuring dual-unit cells with symmetric mirror structures, where each unit cell includes a select gate, P+ source doped region, and P+ drain/source doped region, with floating gates for improved data retention and error correction, allowing for independent programming and reduced current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single PMOS transistor with floating gate is used for memory storage, then the device structure is simple and process compatibility is good, but data correctness is insufficient
Solution Approach 1:
The memory cell is segmented into two separate PMOS transistors (first PMOS transistor with first floating gate and second PMOS transistor with second floating gate) instead of using a single transistor. Each transistor independently stores data bits, and their combined state provides enhanced data correctness through redundant storage and verification capability, directly resolving the contradiction between reliability and simplicity.
2Reliability
If higher data correctness is required with strict error requirements, then data reliability improves, but the existing memory cell structure cannot meet the requirements
Solution Approach 1:
By dividing the memory function across two independent PMOS transistors with separate floating gates, the system achieves enhanced data correctness through redundant storage. The segmented architecture allows flexible programming schemes (such as programming one transistor first, then the other) and provides adaptability to different process variations, meeting both reliability and versatility requirements.
Solution Approach 2:
The invention utilizes different voltage parameters (first programming voltage, second programming voltage, first read voltage, second read voltage) applied to the two PMOS transistors to achieve enhanced data correctness. By independently controlling voltage parameters for each transistor during programming and reading operations, the system can tolerate process variations and achieve higher data reliability while maintaining process flexibility.
3Reliability
If electrons are selectively injected and stored in the floating gate during writing operation, then data storage is achieved, but charge retention problems occur in some memory cells
Solution Approach 1:
The charge storage function is segmented across two separate floating gates (first floating gate and second floating gate) in two independent PMOS transistors. This segmentation provides redundant charge storage paths, so if charge retention degrades in one transistor due to process variations, the other transistor can compensate, thereby improving overall charge retention ability while maintaining ease of manufacture through standard CMOS processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dual-unit cell design enhances data correctness and reduces current consumption, improving reliability and compatibility with logic processes while maintaining low-voltage operation.
Implementation Method 1
During writing operation, electrons are selectively injected and stored in the floating gate 6
Data Source
AI summary
A non-volatile single-poly memory device is disclosed. The non-volatile single-poly memory device includes two mirror symmetric unit cells, which is capable of providing improved data correctness. Further, the non-volatile single-poly memory device is operated at low voltages and is fully compatible with logic processes.