Nonvolatile SRAM Cell Mode Switching for Power Reduction
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Solution Overview
Problem
Conventional SRAM used in microprocessors as cache memory requires significant static power due to leak current, which increases with miniaturization, leading to high power consumption.
Innovation Solution
A nonvolatile SRAM cell configuration utilizing a magnetic tunnel junction (MTJ) and transistors, allowing the SRAM to switch between SRAM mode for high-speed operation and store mode to reduce power consumption by storing data in the MTJ when not accessed, using resistance states to manage power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional SRAM is used for cache memory to achieve high-speed operation, then data access speed is improved, but static power consumption increases due to leak current
Solution Approach 1:
The SRAM cell dynamically switches between two operational modes: SRAM mode for high-speed data access and MRAM mode for low-power data storage. The mode switching is controlled by a mode control signal that adjusts the circuit configuration, allowing the system to adapt between speed and power consumption based on operational requirements
Solution Approach 2:
The patent changes the operational parameters of the SRAM cell by transitioning it between SRAM and MRAM modes. This involves modifying the circuit connectivity and operational characteristics through mode control signals, enabling the same physical structure to exhibit different performance characteristics (speed vs. power consumption)
2Productivity
If SRAM is used to maintain high-speed data access, then productivity is improved, but power consumption increases due to continuous power supply requirements
Solution Approach 1:
The system dynamically adapts its operational state based on productivity needs. When high throughput is required, the SRAM mode provides fast access; when throughput requirements are lower, the system can transition to MRAM mode to reduce power consumption, optimizing the balance between productivity and energy usage
3Area of stationary object
If miniaturization is pursued to increase integration density, then area is reduced, but leak current increases causing higher static power
Solution Approach 1:
The miniaturized SRAM cell incorporates dynamic mode switching capability that allows it to operate in low-power MRAM mode when data is not frequently accessed. This dynamic adaptation compensates for the increased leak current inherent in miniaturized structures, maintaining acceptable power consumption despite the reduced dimensions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The nonvolatile SRAM cell achieves reduced power consumption by minimizing leak current when not in use, maintaining data integrity and enabling high-speed data access, thus addressing the power efficiency challenges of conventional SRAM.
Implementation Method 1
a nonvolatile SRAM cell configuration utilizing a magnetic tunnel junction (MTJ) and transistors, allowing the SRAM to switch between SRAM mode for high-speed operation and store mode to reduce power consumption by storing data in the MTJ when not accessed, using resistance states to manage power usage
Data Source
AI summary
In one embodiment, there is provided a semiconductor integrated circuit that includes: a first inverter; a second inverter; a first transistor, wherein one end of the first transistor is connected to a first bit line and the other end of the first transistor is connected to a first input terminal of the first inverter; a first element group including second transistors, wherein one end of the first element group is connected to a first output terminal of the first inverter and the other end of the first element group is connected to a second bit line; and a second element group including third transistors and a magnetoresistive element whose magnetic resistance is varied. The second element group is disposed between the second output terminal of the second inverter and a first terminal or disposed between the first transistor and the first terminal.