Non-volatile SRAM Cell with Embedded Charge Trap Transistors
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Solution Overview
Problem
Existing SRAM cells are volatile, losing data when power is off, and standalone charge trap transistor (CTT) arrays incur high overhead and separate peripheral costs, lacking integration with SRAM cells for combined high-speed and non-volatile storage.
Innovation Solution
Incorporating a latch circuit with non-volatile field effect transistors (FETs) connected to bit lines and wordlines, allowing for data writing and reading by changing threshold voltages and using differential sensing, thereby embedding CTTs within SRAM cells to enhance memory density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standalone charge trap transistor (CTT) arrays are used for non-volatile storage, then non-volatile storage capability is achieved, but area overhead and peripheral costs increase significantly
Solution Approach 1:
The patent merges the CTT storage array with the SRAM cell structure by integrating CTTs as access transistors within the SRAM cell itself. This combination allows the same transistor to serve dual purposes: providing non-volatile storage functionality while simultaneously acting as the access transistor for SRAM operations, thereby eliminating the need for separate standalone CTT arrays and reducing overall area overhead.
Solution Approach 2:
The CTTs in the patent are designed to perform multiple functions: they serve as non-volatile storage elements, act as access transistors for SRAM cell operations, and function as part of the latch circuit. This multi-functionality allows a single component to replace what would traditionally require separate dedicated structures, thereby reducing area overhead and peripheral costs.
2Speed
If separate SRAM and CTT arrays are used, then high-speed SRAM operation is maintained, but peripheral costs and device complexity increase
Solution Approach 1:
The patent combines SRAM and CTT arrays into a unified structure where CTTs are embedded within SRAM cells. This merger allows the system to maintain high-speed SRAM operation while reducing peripheral complexity, as the integrated structure shares common control logic, bit lines, and word lines between the SRAM and non-volatile storage functions.
Solution Approach 2:
The access transistors (CTTs) perform multiple functions including serving as storage elements, access transistors, and part of the latch circuit. This multi-functionality reduces the need for separate peripheral circuits and control logic, thereby reducing device complexity and peripheral costs while maintaining high-speed operation.
3Speed
If traditional volatile SRAM cells are used, then high-speed writing and reading is achieved, but data is lost when power is turned off
Solution Approach 1:
The patent utilizes threshold voltage modulation of the CTTs to encode and retain data. By changing the threshold voltage parameter of the CTTs through programming operations, data is stored in a non-volatile manner that persists when power is turned off, while maintaining the ability to perform high-speed read operations by sensing the threshold voltage state.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This integration reduces area overhead, improves memory density, and enables near-memory computing by allowing data storage and retrieval in SRAM cells with reduced peripheral costs, combining the benefits of high-speed SRAM and non-volatile storage.
Implementation Method 1
writing data in at least one non-volatile field effect transistor (FET) of a memory bitcell circuit by changing a threshold voltage of the at least one non-volatile FET
Implementation Method 2
reading the data in the at least one non-volatile FET of the memory bitcell circuit by using differential sensing of the at least one non-volatile FET
Data Source
AI summary
The present disclosure relates to a structure including a latch circuit, a first non-volatile field effect transistor (FET) connecting to a first side of the latch circuit and a bit line, and a second non-volatile field effect transistor (FET) connecting to a second side of the latch circuit and a complementary bit line.