Non-Volatile SRAM With Multiple MTJ Cells for Faster Access
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Solution Overview
Problem
Existing memory devices face challenges in achieving fast read and write speeds while maintaining high storage density, particularly in non-volatile memory devices like magnetic tunnel junction (MTJ) cells, which are slower than volatile SRAM.
Innovation Solution
Integrating static random access memory (SRAM) with multiple magnetic tunnel junction (MTJ) cells, utilizing a shared amplifier configuration and pipelining to enhance reading and writing speeds, and employing asymmetrical data storage through reference MTJ cells to increase storage density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If non-volatile memory devices like MTJ cells are used, then data retention without power is achieved, but read and write speeds are slower compared to volatile memory
Solution Approach 1:
The patent merges SRAM cells and MTJ cells into a hybrid memory architecture where SRAM cells serve as amplifiers and buffers for MTJ cells. This combination allows the system to leverage the fast access speed of SRAM for read operations while maintaining the non-volatile storage capability of MTJ cells, thereby resolving the contradiction between speed and retention.
Solution Approach 2:
SRAM cells act as intermediaries between the control circuitry and MTJ cells. The SRAM amplifiers buffer and condition signals before they reach the MTJ cells, enabling faster and more reliable read and write operations. This intermediary layer translates the slow MTJ access into faster effective operations from the perspective of the control logic.
2Quantity of substance
If storage density is increased, then more data can be stored in a smaller area, but read and write operations become slower due to increased access complexity
Solution Approach 1:
The memory array is segmented into multiple blocks, each containing both SRAM and MTJ cells. This segmentation allows parallel access to different blocks simultaneously, maintaining high storage density while preserving read and write speeds through concurrent operations across multiple segments.
Solution Approach 2:
The SRAM cells serve multiple functions: they act as amplifiers for reading MTJ cell states, as write drivers for programming MTJ cells, and as temporary storage buffers. This multi-functionality allows the system to maintain high storage density without sacrificing access speed, as the same components handle multiple operations efficiently.
3Ease of operation
If symmetrical data storage is used in MTJ cells, then simple read operations are achieved, but storage density is limited
Solution Approach 1:
The patent employs asymmetrical data storage schemes where data is stored in a non-symmetric manner across MTJ cells, allowing two bits to be stored per cell pair. This asymmetry increases storage density while the SRAM amplifier layer maintains simple read operations by buffering and conditionally accessing the asymmetric storage structure.
Solution Approach 2:
The system transitions from storing data in a single dimension (one bit per MTJ cell) to a multi-dimensional approach where multiple bits are stored across cell pairs using asymmetric configurations. The SRAM layer provides the necessary control to access this additional dimension while maintaining operational simplicity for the reading process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables faster read and write operations with improved storage density by leveraging SRAM's speed and MTJ cells' storage capabilities, doubling storage density through asymmetrical data storage.
Implementation Method 1
magnetic tunnel junction (MTJ) cells
Data Source
AI summary
Disclosed herein is an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.