Nonvolatile SRAM Using RRAM Segmentation for Low Power Retention
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Solution Overview
Problem
SRAM memory cells are volatile, leading to data loss when power is removed and consume energy to maintain states, which is inefficient, especially in battery-powered systems where transitioning to low power states is necessary to conserve energy.
Innovation Solution
Integration of a pair of nonvolatile RRAM memory cells with a volatile SRAM memory cell to provide on-chip storage, using resistive memory elements that can maintain data states without power, reducing the need for frequent data copying to off-chip nonvolatile storage and minimizing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If SRAM memory cells are used for volatile storage, then fast access speed is achieved, but data is lost when power is removed and energy is consumed to maintain states
Solution Approach 1:
The memory system is segmented into two distinct parts: volatile SRAM memory cells for fast access during active operation, and nonvolatile RRAM memory cells for data retention during low power states. This segmentation allows each component to operate in its optimal mode - SRAM provides high-speed access when powered, while RRAM preserves data without power, resolving the contradiction between speed and energy loss.
Solution Approach 2:
The patent merges volatile SRAM and nonvolatile RRAM into a hybrid memory structure where both technologies coexist and complement each other. The SRAM handles high-speed read/write operations during active states, while the RRAM provides nonvolatile data retention, combining the advantages of both volatile and nonvolatile memory to reduce overall energy consumption while maintaining fast access capability.
2Reliability
If data is copied to off-chip nonvolatile storage before entering low power state, then data integrity is preserved, but latency is introduced
Solution Approach 1:
The solution moves from a single-dimension approach (off-chip storage) to a two-dimension approach by integrating nonvolatile RRAM memory cells directly on the same chip as the SRAM. This spatial dimensionality change reduces the physical distance data must travel, eliminating the latency associated with off-chip access while maintaining data integrity during low power transitions.
Solution Approach 2:
The on-chip RRAM memory cells act as an intermediary between the SRAM and external off-chip storage. Instead of directly copying data to distant off-chip storage, the RRAM cells serve as a local buffer that can quickly assume data states from SRAM and hold them during low power states, significantly reducing the time required for data preservation compared to off-chip operations.
3Loss of energy
If frequent transitions between active and low power states are made, then energy efficiency is improved, but data loss risk increases with volatile SRAM
Solution Approach 1:
Before transitioning to a low power state, the system performs a preliminary action by copying data from the volatile SRAM to the nonvolatile RRAM memory cells. This preliminary data transfer ensures that data is safely stored in the nonvolatile medium before power is reduced, eliminating the risk of data loss during subsequent power transitions and enabling frequent state changes without compromising reliability.
Solution Approach 2:
The system changes the operational parameters of the memory subsystem dynamically - during active states, the SRAM is powered and operates at high speed, while during low power states, the RRAM maintains data retention with minimal or no power. This parameter switching between volatile and nonvolatile modes allows frequent transitions while preserving data integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient energy management by allowing SRAM memory cells to enter low power states quickly while preserving data integrity, reducing power consumption and latency associated with off-chip storage, and supporting frequent transitions between active and low power states.
Implementation Method 1
Each resistive memory element has two states: a high resistance state (HRS) and a low resistance state (LRS)
Data Source
AI summary
One embodiment provides an apparatus. The apparatus includes a pair of nonvolatile resistive random access memory (RRAM) memory cells coupled to a volatile static RAM (SRAM) memory cell. The pair of nonvolatile RRAM memory cells includes a first RRAM memory cell and a second RRAM memory cell. The first RRAM memory cell includes a first resistive memory element coupled to a first bit line, and a first selector transistor coupled between the first resistive memory element and a first output node of the volatile SRAM memory cell. The second RRAM memory cell includes a second resistive memory element coupled to a second bit line, and a second selector transistor coupled between the second resistive memory element and a second output node of the volatile SRAM memory cell.