Non-volatile SRAM Cell Using Variable Resistance Memory
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Solution Overview
Problem
Existing programmable logic devices (PLDs) like FPGAs rely on volatile SRAM cells, leading to loss of programmed states upon power-off unless an auxiliary power source is used, and non-volatile memory solutions like EEPROM or flash cells are costly and complex to integrate.
Innovation Solution
A non-volatile static random access memory (SRAM) cell is developed using a variable resistance random access memory cell coupled with a control gate between a charge node and a voltage bus, allowing for the restoration of logic states without reprogramming after power cycling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If volatile SRAM cells are used in FPGAs, then fast access times and standard SRAM performance are achieved, but data is lost upon power-off requiring auxiliary power sources
Solution Approach 1:
The patent combines a conventional SRAM cell with a variable resistance memory cell in a unified memory structure. The SRAM cell provides fast access during operation while the variable resistance cell maintains the stored state non-volately after power-off, effectively merging the advantages of both volatile and non-volatile memory technologies into a single hybrid cell architecture.
Solution Approach 2:
The patent utilizes the resistance state of the variable resistance memory cell to encode and retain logic states. By changing the resistance parameter of the variable resistance cell between two stable states, the system achieves non-volatile data retention while maintaining SRAM-like access speeds through the coupled SRAM cell's rapid read/write capability.
2Reliability
If EEPROM or flash memory cells are used for non-volatile storage, then data retention without power is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent employs a variable resistance memory cell that utilizes resistance state changes to store data non-volately. This approach avoids the complex double polycrystalline silicon cell structures required for EEPROM and flash memory, achieving non-volatile storage with simpler manufacturing processes that are more compatible with standard CMOS logic fabrication.
Solution Approach 2:
By integrating the variable resistance memory cell directly with the SRAM cell structure, the patent creates a unified memory unit that provides non-volatile storage without requiring separate EEPROM or flash memory blocks. This merging approach reduces overall device complexity and eliminates the need for additional complex memory integration steps.
Data Source
AI summary
A non-volatile static random access memory (“SRAM”) cell using variable resistance random access memory (“RAM”) cells is described. A memory tri-cell includes an SRAM cell with a first charge node and a second charge node. A first variable resistance random access memory cell is coupled between the first charge node and a supply voltage bus. A second variable resistance random access memory cell is coupled between the first charge node and a ground bus. A first control gate is coupled between the supply voltage bus and the first variable resistance random access memory cell. A second control gate is coupled between the ground bus and the second variable resistance random access memory cell.