Nonvolatile Storage Control Circuit Partitioning for Pin Reduction
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Solution Overview
Problem
Increasing the number of nonvolatile semiconductor storage devices while maintaining a compact control circuit size and ensuring efficient data transfer is challenging, as adding more chips requires more pins for signal coupling, leading to larger control circuits or reduced chip connectivity.
Innovation Solution
A nonvolatile semiconductor storage system with multiple nonvolatile semiconductor media, a control circuit, and switches that partition data into elements and distribute them across multiple chips via data buses, allowing efficient data transfer without the need for additional connectors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of nonvolatile chips is increased to increase storage capacity, then storage capacity is improved, but the control circuit size becomes larger due to more pins required for signal coupling
Solution Approach 1:
The patent divides the control circuit into a host interface unit and multiple channel units. Each channel unit can independently control a subset of nonvolatile chips, segmenting the monolithic control circuit into modular components. This segmentation reduces the pin count required in any single control circuit while maintaining the ability to control multiple chips across distributed channel units.
Solution Approach 2:
The patent introduces a hierarchical control structure with multiple abstraction levels: host interface unit at the top level and channel units at lower levels. This dimensional organization allows the system to manage numerous chips without requiring a proportionally large single control circuit, effectively distributing control functions across multiple dimensions of the system architecture.
2Device complexity
If the control circuit size is made smaller, then device complexity is reduced, but the number of nonvolatile chips that can be coupled decreases
Solution Approach 1:
Each channel unit is designed as a universal module capable of controlling multiple nonvolatile chips through shared data buses. The channel units can be replicated and configured to handle different numbers and types of chips, providing multi-functional capability that allows a smaller control circuit to manage a large total number of chips across the system.
Solution Approach 2:
The patent introduces channel units as intermediary components between the host interface unit and the nonvolatile chips. These channel units act as mediators that manage data transfer and control signals, allowing the host interface to control numerous chips indirectly through the channel layer, thereby reducing the direct pin requirements at the host interface while maintaining comprehensive chip control.
3Quantity of substance
If large numbers of nonvolatile chips are coupled to increase storage capacity, then storage capacity is improved, but data transfer efficiency deteriorates due to increased complexity in managing multiple chips
Solution Approach 1:
The patent segments data transfer operations into multiple independent channels, each handled by a dedicated channel unit. This segmentation allows parallel data transfer to multiple chips simultaneously, maintaining high throughput even as the total number of chips increases. Each channel operates independently, preventing bottlenecks that would occur in a centralized transfer architecture.
Solution Approach 2:
The channel units are designed to continuously manage data transfer operations without interruption, even as multiple chips are accessed. The architecture enables overlapping and parallel transfer operations across different channels, ensuring that data transfer efficiency is maintained continuously rather than being interrupted by the complexity of managing numerous chips sequentially.
Data Source
AI summary
A nonvolatile semiconductor storage system has multiple nonvolatile semiconductor storage media, a control circuit having a media interface group (one or more interface devices) coupled to the multiple nonvolatile semiconductor storage media, and multiple switches. The media interface group and the multiple switches are coupled via data buses, and each switch and each of two or more nonvolatile chips are coupled via a data bus. The switch is configured so as to switch a coupling between a data bus coupled to the media interface group and a data bus coupled to any of multiple nonvolatile chips that are coupled to this switch. The control circuit partitions write-target data into multiple data elements, switches a coupling by controlling the multiple switches, and distributively sends the multiple data elements to multiple nonvolatile chips.