Nonvolatile Storage Device Copy Mode Management
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Solution Overview
Problem
The existing methods for writing data in NAND-type flash memory require varying processing times due to differences between normal and chip copy operations, leading to inconsistent data writing times and increased buffer capacity needs, which in turn increase costs.
Innovation Solution
A nonvolatile storage device with a memory controller that employs multiple copy modes, including error correction and non-error correction methods, to manage data copying across blocks, ensuring consistent processing times and reduced buffer capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If normal copy with error correction is performed, then data reliability is improved, but processing time increases
Solution Approach 1:
The patent implements periodic error correction by performing normal copy with error correction at predetermined intervals (when copy count reaches a threshold) while using faster chip copy without error correction for intermediate copies. This periodic application of error correction maintains data reliability over time while minimizing the impact on overall processing speed.
Solution Approach 2:
The system dynamically switches between two copy modes (chip copy without error correction and normal copy with error correction) based on the copy count. The memory controller adjusts the copy method dynamically, using faster chip copy when copy count is below the threshold and switching to normal copy with error correction when the threshold is reached, thereby optimizing both speed and reliability.
2Loss of time
If chip copy without error correction is used, then processing time is reduced, but data reliability deteriorates
Solution Approach 1:
Error correction is performed periodically at predetermined intervals rather than continuously. The system uses chip copy without error correction for most operations to maintain speed, then performs normal copy with error correction when the copy count reaches a predetermined threshold, ensuring reliability without constant overhead.
Solution Approach 2:
The system dynamically selects the copy method based on the current copy count relative to a predetermined threshold. When the copy count is below the threshold, chip copy without error correction is used for speed. When the threshold is reached, the system switches to normal copy with error correction to ensure data reliability, then resets the count.
3Productivity
If buffer capacity is increased to handle writing time variation, then real-time writing capability is improved, but device cost increases
Solution Approach 1:
The patent changes the parameter of copy processing time by implementing a hybrid copy strategy that combines fast chip copy with periodic normal copy. This parameter change equalizes the overall writing time across different blocks by ensuring that error correction is performed regularly, preventing large time variations that would otherwise require large buffers.
Solution Approach 2:
By performing error correction periodically rather than continuously or never, the system creates a more predictable and equalized writing time pattern. This periodic error correction ensures that no single block accumulates excessive correction time, thereby equalizing overall writing times and reducing the buffer capacity needed to handle variations.
Data Source
AI summary
Upon copying data stored on a page in a copy source block of a nonvolatile memory to a page of a copy destination block, an access control unit of a memory controller copies data stored on a page associated with a first copy method to a page of the copy destination block after error correction by an error correction control unit copies data stored on a page associated with a second copy method to a page of the copy destination block without performing the error correction by the error correction control unit according to a copy mode stored in a copy mode storage area, and changes the copy mode associated with the copy destination block to a copy mode that is different from the copy mode of the copy source block.


