Non-volatile Semiconductor Storage Forming Method
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Solution Overview
Problem
The forming process in non-volatile semiconductor storage devices, which involves transitioning a variable resistor element from an insulating state to a conductive state, is time-consuming and inefficient when applied to multiple bits simultaneously due to the low current flow and voltage application challenges.
Innovation Solution
A non-volatile semiconductor storage device configuration that multiple-selects word lines and bit lines using a control unit to apply a forming potential, allowing for simultaneous formation of multiple memory cells by managing the potential states of word and bit lines through decoder circuits and connection circuits, thereby optimizing the forming process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If forming voltage is applied to a single variable resistor element at a time, then the resistance state can be reliably switched, but the process time becomes excessively long when multiple bits need to be formed
Solution Approach 1:
The patent segments the forming process into two distinct phases: a first forming process that applies voltage to all selected word lines simultaneously to create initial conductive paths, and a second forming process that applies voltage only to unformed memory cells. This segmentation allows reliable formation of multiple bits by dividing the complex task into manageable stages, preventing voltage application errors while maintaining high productivity.
Solution Approach 2:
The patent performs a preliminary forming action by applying voltage to all selected word lines in the first forming process before performing individual cell verification and additional forming in the second process. This preliminary action ensures that potential conductive paths are established across all selected cells simultaneously, enabling subsequent precise control and reducing the need for repeated individual forming operations.
2Productivity
If high voltage is applied to multiple variable resistor elements simultaneously, then forming speed increases, but voltage control precision decreases leading to formation errors in non-selected cells
Solution Approach 1:
The patent applies local quality by using different voltage levels and control strategies for different groups of memory cells. Selected word lines receive forming voltage during the first forming process, while non-selected word lines are held at a different potential. During the second forming process, only specific unformed cells receive additional voltage. This localized voltage application ensures high productivity through simultaneous multi-cell processing while maintaining precise control to prevent errors in non-selected cells.
Solution Approach 2:
The patent employs dynamic voltage control where the voltage state of word lines changes based on the formation status of memory cells. During the first forming process, all selected word lines are dynamically set to forming voltage. During the second process, voltages are dynamically adjusted based on read verification results, applying voltage only to cells that remain unformed. This dynamic adaptation maintains precision while enabling parallel processing of multiple cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the time required for the forming step by efficiently applying the forming voltage to multiple memory cells, improving the speed and efficiency of the process while ensuring accurate formation of resistance states.
Implementation Method 1
the variable resistor element becomes lower resistance and the current of a few μA is flowed when forming is carried out
Data Source
AI summary
According to one embodiment, a control unit multiple-selects a first line for every N lines from a plurality of first lines. N is an integer greater than or equal to one. The control unit sets the multiple-selected first lines to a selection potential, and fixes potentials of non-selected first lines at least adjacent to the multiple-selected first lines at a first timing. The control unit causes the multiple-selected first lines to be in a floating state at a second timing after the first timing. The control unit selects one second line from the plurality of second lines and sets the one second line to a forming potential at a third timing after the second timing.